SBOS729B October   2015  – October 2025 DRV425

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Fluxgate Sensor Front-End
        1. 6.3.1.1 Fluxgate Sensor
        2. 6.3.1.2 Bandwidth
        3. 6.3.1.3 Differential Driver for the Internal Compensation Coil
        4. 6.3.1.4 Magnetic Field Range, Overrange Indicator, and Error Flag
      2. 6.3.2 Shunt-Sense Amplifier
      3. 6.3.3 Voltage Reference
      4. 6.3.4 Low-Power Operation
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Linear Position Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Current Sensing in Busbars
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power Supply Decoupling
      2. 7.3.2 Power-On Start-Up and Brownout
      3. 7.3.3 Power Dissipation
        1. 7.3.3.1 Thermal Pad
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.4 Low-Power Operation

In applications with low-bandwidth or low sample-rate requirements, significantly reduce the average power dissipation of the DRV425 by powering down the device between measurements. The DRV425 requires 300μs to fully settle the analog output VOUT, as shown in Figure 6-6. To minimize power dissipation, power down the device immediately after the ADC acquires the sample.

DRV425 Settling Time of the DRV425 VOUT OutputFigure 6-6 Settling Time of the DRV425 VOUT Output