SBVS466 November   2025 TPS7N49

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Shutdown
      2. 6.3.2 Active Discharge
      3. 6.3.3 Power-Good Output (PG)
      4. 6.3.4 Internal Current Limit
      5. 6.3.5 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Dropout Voltage
      3. 7.1.3 Output Noise
      4. 7.1.4 Estimating Junction Temperature
      5. 7.1.5 Soft-Start, Sequencing, and Inrush Current
      6. 7.1.6 Power-Good Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.2 Active Discharge

The TPS7N49 has an internal active pulldown circuits on the OUT pin.

Each active discharge function uses an internal metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET connects a resistor (RPULLDOWN) to ground when the low-dropout resistor (LDO) is disabled to actively discharge the output voltage. The active discharge circuit is activated when the device is disabled by driving EN to logic low. The circuit is also activated when the voltage at IN or BIAS is below the UVLO threshold, or when the regulator is in thermal shutdown.

The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the pulldown resistor.

The first active pulldown circuit connects the output to GND through a 600Ω resistor when the device is disabled.

The second circuit connects FB to GND through a 120Ω resistor when the device is disabled. This resistor discharges the FB pin. Equation 1 calculates the output capacitor discharge time constant when OUT is shorted to FB, or when the output voltage is set to 0.65V.

Equation 1. τOUT = (600 || 120 × RL / (600 || 120 + RL) × COUT

If the LDO is set to an output voltage greater than 0.65V, a resistor divider network is in place and minimizes the FB pin pulldown. Equation 2 and Equation 3 calculate the time constants set by these discharge resistors.

Equation 2. RDISCHARGE = (120 || R2) + R1
Equation 3. τOUT = RDISCHARGE × RL / (RDISCHARGE + RL) × COUT

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply collapses. Reverse current potentially flows from the output to the input and causes damage to the device. Limit reverse current to no more than 5% of the device-rated current.