The following images illustrate the functions of R_θJA and ψ_JB versus copper area and thickness for the HSOIC-8 (DDA) package. These plots are generated with a 101.6mm × 101.6mm × 1.6mm printed circuit board (PCB) of two and four layers. For the 2-layer board, the bottom layer is a ground plane of constant size, and the top layer copper is connected to GND and varied. For the 4-layer board, the second layer is a ground plane of constant size and the third layer is a power plane of constant size. The top and bottom layers copper fills are connected to GND and varied at the same rate. For the 4-layer board, inner planes use 1oz copper thickness. Outer layers are simulated with both 1oz and 2oz copper thickness. A 3 × 3 array of thermal vias with a 300µm drill diameter and 25µm copper plating is located underneath the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. PowerPAD™ Thermally Enhanced Package application note discusses the impact that thermal vias have on thermal performance.

Figure 7-2 R_θJA vs Copper Area (HSOIC-8 Package, 2 Layer PCB)

Figure 7-4 R_θJA vs Copper Area (HSOIC-8 Package, 4 Layer PCB)

Figure 7-3 ψ_JB vs Copper Area (HSOIC-8 Package, 2 Layer PCB)

Figure 7-5 ψ_JB vs Copper Area (HSOIC-8 Package, 4 Layer PCB)