SCAS891A February   2010  – May 2025 CDCE949-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Resistance Characteristics
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Recommended Crystal/VCXO Specifications
    6. 5.6  EEPROM Specification
    7. 5.7  Electrical Characteristics
    8. 5.8  Timing Requirements
      1. 5.8.1 CLK_IN Timing Requirements
      2. 5.8.2 SDA/SCL Timing Requirements
    9. 5.9  Timing Diagrams
      1. 5.9.1 Timing Diagram for the SDA/SCL Serial Control Interface
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
      5. 7.3.5 PLL Multiplier/Divider Definition
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
      1. 7.5.1 Generic Programming Sequence
      2. 7.5.2 Byte Write Programming Sequence
      3. 7.5.3 Byte Read Programming Sequence
      4. 7.5.4 Block Write Programming Sequence
      5. 7.5.5 Block Read Programming Sequence
  9. 8 Register Maps
    1. 8.1 SDA and SCL Registers
    2. 8.2 Configuration Registers
      1. 8.2.1 Generic Configuration Register
      2. 8.2.2 PLL1 Configuration Register
      3. 8.2.3 PLL2 Configuration Register
      4. 8.2.4 PLL3 Configuration Register
      5. 8.2.5 PLL4 Configuration Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.1 Control Terminal Configuration

The CDCE949 has three user-definable control terminals (S0, S1 and S2) which allow external control of device settings. The terminals can be programmed to perform any of the following functions:

  • Spread-Spectrum Clocking selection: Spread-type and spread-amount selection
  • Frequency selection: Switching between any of two user-defined frequencies
  • Output-State selection: Output configuration and power-down control

The user can predefine up to eight different control settings. Table 7-1 and Table 7-2 explain these settings.

Table 7-1 Control Terminal Definition
External Control-Bits PLL1 Setting PLL2 Setting PLL3 Setting PLL4 Setting Y1 Setting
Control Function PLL Frequency Selection SSC Selection Output Y2/Y3 Selection PLL Frequency Selection SSC Selection Output Y4/Y5 Selection PLL Frequency Selection SSC Selection Output Y6/Y7 Selection PLL Frequency Selection SSC Selection Output Y8/Y9 Selection Output Y1 and Power Down Selection
Table 7-2 PLLx Setting (Can be Selected for Each PLL Individual)(1)
SSC Selection (Center/Down)
SSCx [3-bits] Center Down
0 0 0 0% (off) 0% (off)
0 0 1 ±0.25% –0.25%
0 1 0 ±0.5% –0.5%
0 1 1 ±0.75% –0.75%
1 0 0 ±1.0% –1.0%
1 0 1 ±1.25% –1.25%
1 1 0 ±1.5% –1.5%
1 1 1 ±2.0% –2.0%
FREQUENCY SELECTION(2)
FSx FUNCTION
0 Frequency0
1 Frequency1
OUTPUT SELECTION(3) (Y2 ... Y9)
YxYx FUNCTION
0 State0
1 State1
(1) Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register;
(2) Frequency0 and Frequency1 can be any frequency within the specified fVCO range.
(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down, 3-state, low or active
Table 7-3 Y1 Setting(1)
Y1 SELECTION
Y1FUNCTION
0State 0
1State 1
(1) State0 and State1 are user-definable in Generic Configuration Register and can be power down, 3-state, low or active.

The S1/SDA and S2/SCL pins of the CDCE949 are dual-function pins. In the default configuration the pins are defined as SDA/SCL for the serial interface. The pins can be programmed as control pins (S1/S2) by setting the appropriate bits in the EEPROM. Note that changes to the Control register (Bit [6] of Byte 02) have no effect until the changes are written into the EEPROM.

Once the pins are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporarily act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin, this pin is a control pin only.