SCAS891A February   2010  – May 2025 CDCE949-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Resistance Characteristics
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Recommended Crystal/VCXO Specifications
    6. 5.6  EEPROM Specification
    7. 5.7  Electrical Characteristics
    8. 5.8  Timing Requirements
      1. 5.8.1 CLK_IN Timing Requirements
      2. 5.8.2 SDA/SCL Timing Requirements
    9. 5.9  Timing Diagrams
      1. 5.9.1 Timing Diagram for the SDA/SCL Serial Control Interface
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
      5. 7.3.5 PLL Multiplier/Divider Definition
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
      1. 7.5.1 Generic Programming Sequence
      2. 7.5.2 Byte Write Programming Sequence
      3. 7.5.3 Byte Read Programming Sequence
      4. 7.5.4 Block Write Programming Sequence
      5. 7.5.5 Block Read Programming Sequence
  9. 8 Register Maps
    1. 8.1 SDA and SCL Registers
    2. 8.2 Configuration Registers
      1. 8.2.1 Generic Configuration Register
      2. 8.2.2 PLL1 Configuration Register
      3. 8.2.3 PLL2 Configuration Register
      4. 8.2.4 PLL3 Configuration Register
      5. 8.2.5 PLL4 Configuration Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.2.3 PLL2 Configuration Register

Table 8-5 PLL2 Configuration Register
OFFSET(1) Bit(2) Acronym Default(3) DESCRIPTION
20h 7:5 SSC2_7 [2:0] 000b SSC2: PLL2 SSC Selection (Modulation Amount)(4)
4:2 SSC2_6 [2:0] 000b Down
000 (off)
001 – 0.25%
010 – 0.5%
011 – 0.75%
100 – 1.0%
101 – 1.25%
110 – 1.5%
111 – 2.0%		 Center
000 (off)
001 ± 0.25%
010 ± 0.5%
011 ± 0.75%
100 ± 1.0%
101 ± 1.25%
110 ± 1.5%
111 ± 2.0%
1:0 SSC2_5 [2:1] 000b
21h 7 SSC2_5 [0]
6:4 SSC2_4 [2:0] 000b
3:1 SSC2_3 [2:0] 000b
0 SSC2_2 [2] 000b
22h 7:6 SSC2_2 [1:0]
5:3 SSC2_1 [2:0] 000b
2:0 SSC2_0 [2:0] 000b
23h 7 FS2_7 0b FS2_x: PLL2 Frequency Selection(4)
6 FS2_6 0b 0 – fVCO2_0 (predefined by PLL2_0 – Multiplier/Divider value)
1 – fVCO2_1 (predefined by PLL2_1 – Multiplier/Divider value)
5 FS2_5 0b
4 FS2_4 0b
3 FS2_3 0b
2 FS2_2 0b
1 FS2_1 0b
0 FS2_0 0b
24h 7 MUX2 1b PLL2 Multiplexer: 0 – PLL2
1 – PLL2 Bypass (PLL2 is in power down)
6 M4 1b Output Y4 Multiplexer: 0 – Pdiv2
1 – Pdiv4
5:4 M5 10b Output Y5 Multiplexer: 00 – Pdiv2-Divider
01 – Pdiv4-Divider
10 – Pdiv5-Divider
11 – reserved
3:2 Y4Y5_ST1 11b Y4, Y5-State0/1definition: 00 – Y4/Y5 disabled to 3-State (PLL2 is in power down)
01 – Y4/Y5 disabled to 3-State (PLL2 on)
10–Y4/Y5 disabled to low (PLL2 on)
11 – Y4/Y5 enabled (normal operation, PLL2 on)
1:0 Y4Y5_ST0 01b
25h 7 Y4Y5_7 0b Y4Y5_x Output State Selection(4)
6 Y4Y5_6 0b 0 – state0 (predefined by Y4Y5_ST0)
1 – state1 (predefined by Y4Y5_ST1)
5 Y4Y5_5 0b
4 Y4Y5_4 0b
3 Y4Y5_3 0b
2 Y4Y5_2 0b
1 Y4Y5_1 1b
0 Y4Y5_0 0b
26h 7 SSC2DC 0b PLL2 SSC down/center selection: 0 – down
1 – center
6:0 Pdiv4 01h 7-Bit Y4-Output-Divider Pdiv4: 0 – reset and stand-by
1-to-127 – divider value
27h 7 — 0b Reserved – do not write others than 0
6:0 Pdiv5 01h 7-Bit Y5-Output-Divider Pdiv5: 0 – reset and stand-by
1-to-127 – divider value
28h 7:0 PLL2_0N [11:4 004h PLL2_0: 30-Bit Multiplier/Divider value for frequency fVCO2_0
(for more information see paragraph PLL Multiplier/Divider Definition)
29h 7:4 PLL2_0N [3:0]
3:0 PLL2_0R [8:5] 000h
2Ah 7:3 PLL2_0R[4:0]
2:0 PLL2_0Q [5:3] 10h
2Bh 7:5 PLL2_0Q [2:0]
4:2 PLL2_0P [2:0] 010b
1:0 VCO2_0_RANGE 00b fVCO2_0 range selection: 00 – fVCO2_0 < 125MHz
01 – 125MHz ≤ fVCO2_0 < 150MHz
10 – 150MHz ≤ fVCO2_0 < 175MHz
11 – fVCO2_0 ≥ 175MHz
2Ch 7:0 PLL2_1N [11:4] 004h PLL2_1: 30-Bit Multiplier/Divider value for frequency fVCO1_1
(for more information see paragraph PLL Multiplier/Divider Definition)
2Dh 7:4 PLL2_1N [3:0]
3:0 PLL2_1R [8:5] 000h
2Eh 7:3 PLL2_1R[4:0]
2:0 PLL2_1Q [5:3] 10h
2Fh 7:5 PLL2_1Q [2:0]
4:2 PLL2_1P [2:0] 010b
1:0 VCO2_1_RANGE 00b fVCO2_1 range selection: 00 – fVCO2_1 < 125MHz
01 – 125MHz ≤ fVCO2_1 < 150MHz
10 – 150MHz ≤ fVCO2_1 < 175MHz
11 – fVCO2_1 ≥ 175MHz
(1) Writing data beyond 50h can adversely affect device function.
(2) All data is transferred MSB-first.
(3) Unless a custom setting is used
(4) The user can pre-define up to eight different control settings. In normal device operation, these settings can be selected by the external control pins, S0, S1, and S2.