SCASE79A April   2025  – September 2025 TPUL2T323

PRODUCTION DATA  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Retriggerable One-Shot
      3. 7.3.3 Extended RC Timed One-Shot
      4. 7.3.4 Balanced CMOS Push-Pull Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Partial Power Down (Ioff)
      8. 7.3.8 Reduced Input Threshold Voltages
      9. 7.3.9 Clamp Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off-State Operation
      2. 7.4.2 Startup Operation
      3. 7.4.3 On-State Operation
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Edge Detector
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Timing Components
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application - Delayed Pulse Generator
      1. 8.3.1 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

8.5.1 Layout Guidelines

  • Timing component placement
    • Place near the device
    • Provide an electrically short path to the device terminal connections
  • Bypass capacitor placement
    • Place near the positive supply terminal of the device
    • Provide an electrically short ground return path
    • Use wide traces to minimize impedance
    • Keep the device, capacitors, and traces on the same side of the board whenever possible
  • Signal trace geometry
    • 8mil to 12mil trace width
    • Lengths less than 12cm to minimize transmission line effects
    • Avoid 90° corners for signal traces
    • Use an unbroken ground plane below signal traces
    • Flood fill areas around signal traces with ground
    • For traces longer than 12cm
      • Use impedance controlled traces
      • Source-terminate using a series damping resistor near the output
      • Avoid branches; buffer signals that must branch separately