SCBA020A October   1999  – March 2020 TMS3705

 

  1.   Integrated TIRIS™ RF Module TMS3705 Introduction to Low-Frequency Reader
    1.     Trademarks
    2. 1 Document Overview
    3. 2 Introduction
    4. 3 Key Features of the TMS3705
      1. 3.1 PLL for the System Clock
      2. 3.2 Ceramic Resonator for Reference Oscillator
      3. 3.3 Full-Bridge Driver Stage
      4. 3.4 Fully Integrated Bandpass Amplifier
      5. 3.5 Multifunctional 2-Wire Interface
    5. 4 Sequence Control
      1. 4.1 Initialization
    6. 5 Circuit Description of the Sample RF Module
      1. 5.1 Oscillator System
      2. 5.2 Antenna Circuit
      3. 5.3 Pre-Amplifier
      4. 5.4 Interface Circuit to the Control Module
      5. 5.5 Antenna Coil
    7. 6 Regulatory Notices and Ordering
      1. 6.1 Regulatory Notices
      2. 6.2 Ordering
  2.   Revision History

5.1 Oscillator System

The reference oscillator for the internal PLL system clock uses a 3-pin ceramic resonator. Those resonators are available with build-in load capacitors so that the capacitors C4 and C5 can be omitted. If a crystal is used, C4 and C5 are required, and their values depend on the crystal itself. The PLL system allows the use of two different reference frequencies, either 4.0 MHz or 2.0 MHz. For a 4-MHz resonator, the F_SEL input must be set to VDD level. For a 2-MHz resonator, the F_SEL input must be set to GND level. If one of these two frequencies is already available in the application and it has logic level outputs, this signal can be fed directly into the OSC1 input.

With the higher frequency tolerance of the ceramic resonator, the 16-MHz system clock also varies more, which changes the transmission rate of the SCIO data output changes in asynchronous mode. If this variation cannot be tolerated by the control module, the data output stage can be set to synchronous mode.