SCDS149B October   2003  – December 2025 SN74CB3T3257

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics 85C
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1.      Related Documentation
      2. 9.1.1 Receiving Notification of Documentation Updates
      3. 9.1.2 Support Resources
      4. 9.1.3 Electrostatic Discharge Caution
      5. 9.1.4 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3 Feature Description

The SN74CB3T3257 features 5Ω switch connection between ports, allowing for low signal loss across the switch. Rail-to-rail switching on data I/O allows for full voltage swing outputs. Ioff supports partial-power-down mode operation, protecting the chip from voltages at output ports when the chip is not powered on. Latch-up performance exceeds 250mA per JESD 17.