3.3-V, 2:1 (SPDT), 4-channel FET bus switch with level shifter
Product details
Parameters
Package | Pins | Size
Features
- Output Voltage Translation Tracks VCC
- Supports Mixed-Mode Signal Operation On All Data I/O Ports
- 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC
- 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC
- 5-V Tolerant I/Os With Device Powered-Up or Powered-Down
- Bidirectional Data Flow, With Near-Zero Propagation Delay
- Low ON-State Resistance (ron) Characteristics (ron = 5
Typical)
- Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical)
- Data and Control Inputs Provide Undershoot Clamp Diodes
- Low Power Consumption (ICC = 20 µA Max)
- VCC Operating Range From 2.3 V to 3.6 V
- Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
- Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 1000-V Charged-Device Model (C101)
- Supports Digital Applications: Level Translation, USB Interface, Memory Interleaving, Bus Isolation
- Ideal for Low-Power Portable Equipment
Description
The SN74CB3T3257 is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3257 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
The SN74CB3T3257 is a 4-bit 1-of-2 multiplexer/demultiplexer with a single output-enable (OE)\ input. The select (S) input controls the data path of the multiplexer/demultiplexer. When OE\ is low, the multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the multiplexer/demultiplexer is disabled, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
Features
- Quick testing of TI's leaded surface mount packages
- Allows leaded suface mount packages to be plugged into 100mil spaced bread board
- Supports TI's 8 most popular leaded packages with a single panel
Design tools & simulation
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
TSSOP (PW) | 16 | View options |
TVSOP (DGV) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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Support & training
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