SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

2.5 Software Overview

Figure 2-5 Generic Flowchart for Software Control of Shift Registers

The software required to control a set of shift registers is relatively simple. Figure 5 provides a generic flowchart that can be used for producing code in any language and with any hardware for GPIO control of shift registers. In this flowchart, there are two loops. The outer loop, shown in blue, repeats for every shift register in the chain. The inner loop, shown in red, repeats for every bit within a shift register. Typically, the number of bits is eight, however it can vary.

The [Read or write bit ‘j’] block is the most important and the most difficult to implement. Please see the example code shown in code example 1 for an approach using an MCU’s built-in SPI module, and the example shown in code example 2 for a direct GPIO control approach.

There is also code provided for the Example Design – Daisy Chain 128 Shift Registers.