SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

1.4 165 Function Shift Registers

The 165 function is an 8-bit parallel-in shift register. The parallel data inputs are logically connected to the internal serial registers. The shift or load (SH/LD) input pin determines the operating state of the device.

In the load mode, the inputs are asynchronously copied into the internal registers. The clock (CLK) and clock inhibit (CLK INH) have no effect in this mode. The QH output will immediately take on the value of data at the H input.

Figure 1-2 Visual Representation of the Primary Operating States for the 165 Function.

In the shift mode, when a rising edge is detected at the CLK or CLK INH input, assuming the opposite input is in the LOW state, the eight registers are loaded with the data value indicated by the arrows in right hand diagram of Figure 1-2. To be clear, the value at SER is loaded into A, while the value that was in A is loaded into B, the value that was in B is loaded into C, and so on. The last value, which was in H (and is accessible at the output QH), is shifted out, or, in other words, it is overwritten.

For normal functionality, the values are loaded into the register, then seven clock pulses are applied to read all eight internal values from the QH output pin.

The output QH comes directly from the last internal shift register, which allows it to be used for daisy-chaining devices together.