SCEA117 July   2022 SN74HCS164 , SN74HCS164-Q1 , SN74HCS165 , SN74HCS165-Q1 , SN74HCS595 , SN74HCS595-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 Types of Shift Registers
    2. 1.2 Default State of a Shift Register
    3. 1.3 164 Function Shift Registers
    4. 1.4 165 Function Shift Registers
    5. 1.5 595 Function Shift Registers
    6. 1.6 Daisy-Chain Two Shift Registers
  4. 2Design Challenges
    1. 2.1 Controller Loading Limits
    2. 2.2 Operating over Large Distances
    3. 2.3 Data Loss Due to Signal Timing
    4. 2.4 Data Rate Limitations
    5. 2.5 Software Overview
  5. 3Example Design - Daisy Chain 72 Shift Registers
    1. 3.1 System Overview
    2. 3.2 System Design
    3. 3.3 Software Examples
  6. 4References

595 Function Shift Registers

Figure 1-3 Visual Representation of the Effect for Each Clock Input of 595 Function Shift Registers

The 595 function includes latched output registers, which allow the serial shift registers to change while holding the outputs constant. Figure 1-3 illustrates the operation of the 595 function. On the rising edge of the SRCLK input, the data at SER will be loaded and the serial registers will shift by one location as indicated by the arrows in the left diagram of Figure 1-3. To be clear, the value at the SER input will be loaded into the first serial register, the value that was in the first serial register will be loaded into the second serial register, the value that was in the second serial register is moved to the third serial register, and so on. The value that was in the last register, which was previously accessible from the QH’ output pin, is “shifted out,” or, in other words, it is overwritten.

On the rising edge of the RCLK input, illustrated in the right diagram of Figure 1-3, the data in the serial registers will be copied to the output registers. The shift registers will still retain the same data in the same locations after this operation is complete.

It is possible to operate this device with SRCLK and RCLK directly shorted together. In this mode of operation, the previous data in the shift registers is first sent to the outputs and then is shifted to the next positions. In this way, the outputs will always be one clock pulse behind the serial register values. To be clear, it will take nine pulses to send eight bits of data to the outputs, and those values will be read into the device with the first eight pulses.

The output QH’ comes directly from the last internal shift register, which allows it to be used for daisy-chaining devices together.