SCES749D September   2009  – June 2025 SN74AUP2G14

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Switching Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delays, Setup and Hold Times, and Pulse Width
    2. 6.2 Enable and Disable Times
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

SN74AUP2G14 DCK Package6 -Pin SC70Top View
See mechanical drawings for dimensions.
Figure 4-1 DCK Package6 -Pin SC70Top View
SN74AUP2G14 DRY Package6-Pin USONTop View Figure 4-2 DRY Package6-Pin USONTop View
SN74AUP2G14 DSF Package6-Pin X2SONTop View Figure 4-3 DSF Package6-Pin X2SONTop View
SN74AUP2G14 YFP Package6-Pin DSBGATop View Figure 4-4 YFP Package6-Pin DSBGATop View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME DCK DRY DSF YFP
1A 1 1 1 A1 II Gate 1 logic signal
GND 2 2 2 B1 — Ground
2A 3 3 3 C1 I Gate 2 logic signal
1Y 6 6 6 A2 O Gate 1 inverted signal
VCC 5 5 5 B2 — Supply/Power Pin
2Y 4 4 4 C2 O Gate 2 inverted signal