SCES749D
September 2009 – June 2025
SN74AUP2G14
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Switching Characteristics
5.8
Switching Characteristics
5.9
Switching Characteristics
5.10
Operating Characteristics
5.11
Typical Characteristics
6
Parameter Measurement Information
6.1
Propagation Delays, Setup and Hold Times, and Pulse Width
6.2
Enable and Disable Times
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
Available in the Texas Instruments
NanoStar™
package
Low static-power consumption
(I
CC
= 0.9μA maximum)
Low dynamic-power consumption
(C
pd
= 4.3pF typical at 3.3V)
Low input capacitance (C
i
= 1.5pF typical)
Low noise – overshoot and undershoot
<10% of V
CC
I
off
supports partial-power-down mode operation
Wide operating V
CC
range of 0.8V to 3.6V
Optimized for 3.3V operation
3.6V I/O tolerant to support mixed-mode signal Operation
t
pd
= 4.3ns maximum at 3.3V
Suitable for point-to-point applications
Latch-up performance exceeds 100mA Per JESD 78, Class II
ESD performance tested per JESD 22
2000V human-body model
(A114-B, Class II)
1000V charged-device model (C101)