SCLA084 October   2025 TPLD1202 , TPLD2001

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Smart LEDs Data and Timing Theory
  6. 3Logic Symbols Generation
  7. 4TPLD-Based Smart LED Controller
  8. 5TPLD Serial Communications
  9. 6Summary
  10. 7References

3 Logic Symbols Generation

An internal 25MHz OSC is generating all the required clock signals including the 12.5MHz by the internal pre-divider OSC/2 that together with counters can generate a time base of 800KHz required by the RGB LED.

Because the clock signal is not symmetrical by design, using TPLD internal delays properly set the T0H and T1H can be generated at 350nS and 800nS, respectively. Controlling the T0L and T1L timing is not required because the required symbol period is actually generated. Figure 3-1 shows the element needed for the time base and symbol generation.

Logic Symbol Generation with TPLD Figure 3-1 Logic Symbol Generation with TPLD

Figure 3-2 shows a screen capture from a logic analyzer of a TPLD device generating all the timing for the logic symbols. A logic multiplexer is used with both symbols as inputs and a select signal generated by other circuit section accordingly to the color that must be generated.

Screenshot of Logic High and Low Symbols Figure 3-2 Screenshot of Logic High and Low Symbols