SCLS117F December   1982  – May 2025 SN54HC166 , SN54HC166-SP , SN74HC166

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6.     12
    7. 5.6 Switching Characteristics
    8. 5.7 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Standard CMOS Inputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted)
VCC(V) TA = 25°C SN54HC166 SN74HC166 UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency 2 6 4.2 5 MHz
4.5 31 21 25
6 36 25 29
tw Pulse duration CLR low 2 100 150 125 ns
4.5 20 30 25
6 17 26 21
CLK high or low 2 80 120 100
4.5 16 24 20
6 14 20 17
tsu Setup time SH/LD high before CLK­↑ 2 145 220 180 ns
4.5 29 44 36
6 25 38 31
SER before CLK­↑ 2 80 120 100
4.5 16 24 20
6 14 20 17
CLK INH low before CLK­↑ 2 100 150 125
4.5 20 30 25
6 17 26 21
Data before CLK­↑ 2 80 120 100
4.5 16 24 20
6 14 20 17
CLR inactive before CLK­↑ 2 40 60 50
4.5 8 12 10
6 7 10 9
th Hold time SH/LD high after CLK­↑ 2 0 0 0 ns
4.5 0 0 0
6 0 0 0
SER after CLK­↑ 2 5 5 5
4.5 5 5 5
6 5 5 5
CLK INH high after CLK­↑ 2 0 0 0
4.5 0 0 0
6 0 0 0
Data after CLK­↑ 2 5 5 5
4.5 5 5 5
6 5 5 5