The SNx4HC166 is a parallel-load 8-bit shift register with asynchronous clear ( CLR). This parallel-in or serial-in, serial-out shift register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the mode select (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (A through H) data inputs are enabled, and synchronous loading occurs on the next clock pulse.

During parallel loading, serial data flow is inhibited. Clocking is accomplished on the rising edge of CLK or CLK INH, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. CLK INH should be changed to the high level only when CLK is high.

CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.