SCLS117F December   1982  – May 2025 SN54HC166 , SN54HC166-SP , SN74HC166

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6.     12
    7. 5.6 Switching Characteristics
    8. 5.7 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Standard CMOS Inputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6 Parameter Measurement Information

tpd is the maximum between tPLH and tPHL

SN54HC166 SN74HC166 Load CircuitFigure 6-1 Load Circuit
SN54HC166 SN74HC166 Voltage WaveformsSetup and Hold and Input Rise and Fall TimesFigure 6-3 Voltage Waveforms
Setup and Hold and Input Rise and Fall Times
SN54HC166 SN74HC166 Voltage WaveformsPulse DurationsFigure 6-2 Voltage Waveforms
Pulse Durations
SN54HC166 SN74HC166 Voltage WaveformsPropagation Delay and Output Transition TimesFigure 6-4 Voltage Waveforms
Propagation Delay and Output Transition Times

A. CL includes probe and jig capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following charactersitics: PRR ≤ 1MHz, ZO = 50Ω, tr = 6ns, tf = 6ns.

C. For clock inputs, fmax is measured when the input duty cycle is 50%

D. The outputs are measured one at a time with one input transition per measurement.