SCLS239P October   1995  – July 2025 SN54AHCT373 , SN74AHCT373

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5.   5
  6. Pin Configuration and Functions
  7. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, VCC = 5V ±0.5V
    7. 5.7  Switching Characteristics, VCC = 5V ±0.5V
    8. 5.8  Noise Characteristics
    9. 5.9  Operating Characteristics
    10. 5.10 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  10. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

SN54AHCT373 SN74AHCT373 
            SN54AHCT373
            
            J 
            , W Package (Top View)Figure 4-1 SN54AHCT373 J , W Package (Top View)
SN54AHCT373 SN74AHCT373 SN54AHCT373
             FK Package (Top View)Figure 4-2 SN54AHCT373 FK Package (Top View)
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
OE 1 I Output enable, active low
1Q 2 O Output for channel 1
1D 3 I Input for channel 1
2D 4 I Input for channel 2
2Q 5 O Output for channel 2
3Q 6 O Output for channel 3
3D 7 I Input for channel 3
4D 8 I Input for channel 4
4Q 9 O Output for channel 4
GND 10 G Ground
LE 11 I Latch enable
5Q 12 O Output for channel 5
5D 13 I Input for channel 5
6D 14 I Input for channel 6
6Q 15 O Output for channel 6
7Q 16 O Output for channel 7
7D 17 I Input for channel 7
8D 18 I Input for channel 8
8Q 19 O Output for channel 8
VCC 20 P Postive supply
Signal Types: I = Input, O = Output, G = Ground, P = Power.
SN54AHCT373 SN74AHCT373 SN74AHCT373 
            RKS Package (Top View)Figure 4-3 SN74AHCT373 RKS Package (Top View)
SN54AHCT373 SN74AHCT373 SN74AHCT373 
            PW, DW, NS, N, DB, DGS Package (Top
            View)Figure 4-4 SN74AHCT373 PW, DW, NS, N, DB, DGS Package
(Top View)
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
OE 1 I Output enable, active low
1Q 2 O Output for channel 1
1D 3 I Input for channel 1
2D 4 I Input for channel 2
2Q 5 O Output for channel 2
3Q 6 O Output for channel 3
3D 7 I Input for channel 3
4D 8 I Input for channel 4
4Q 9 O Output for channel 4
GND 10 G Ground
LE 11 I Latch enable
5Q 12 O Output for channel 5
5D 13 I Input for channel 5
6D 14 I Input for channel 6
6Q 15 O Output for channel 6
7Q 16 O Output for channel 7
7D 17 I Input for channel 7
8D 18 I Input for channel 8
8Q 19 O Output for channel 8
VCC 20 P Postive supply
Thermal Pad(2) The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply.
Signal Types: I = Input, O = Output, G = Ground, P = Power.
RKS package only.