SCLS352I July   1997  – January 2025 SN54AHC123A , SN74AHC123A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics
    6. 4.6  Timing Requirements, VCC = 3.3V ± 0.3V
    7. 4.7  Timing Requirements, VCC = 5 V ± 0.5 V
    8. 4.8  Switching Characteristics, VCC = 3.3V ± 0.3V
    9. 4.9  Switching Characteristics, VCC = 5V ± 0.5V
    10. 4.10 Operating Characteristics
    11. 4.11 Input/Output Timing Diagram
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Caution in Use
      2. 7.1.2 Output Pulse Duration
      3. 7.1.3 Power-down Considerations
      4. 7.1.4 Retriggering Data
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

3 Pin Configuration and Functions

SN54AHC123A SN74AHC123A SN54AHC123A J or W Package; SN74AHC123A D, DB, DGV, N, or PW Package; 16-Pin CDIP, CFP, SOIC, SSOP, TVSOP, PDIP, TSSOP (Top View)Figure 3-1 SN54AHC123A J or W Package; SN74AHC123A D, DB, DGV, N, or PW Package; 16-Pin CDIP, CFP, SOIC, SSOP, TVSOP, PDIP, TSSOP (Top View)
SN54AHC123A SN74AHC123A SN54AHC123A FK Package, 20-Pin LCCC (Top View)Figure 3-2 SN54AHC123A FK Package, 20-Pin LCCC (Top View)
Table 3-1 Pin Functions
PIN I/O1 DESCRIPTION
NAME NO.
1 A 1 I Channel 1 falling edge trigger input when 1B = H; Hold low for other input methods
1B 2 I Channel 1 rising edge trigger input when 1 A = L; Hold high for other input methods
1 CLR 3 I Channel 1 rising edge trigger when 1 A = L and 1B = H; Hold high for other input methods; Can cut pulse length short by driving low during output
1 Q 4 O Channel 1 inverted output
2Q 5 O Channel 2 output
2Cext 6 — Channel 2 external capacitor negative connection
2Rext/Cext 7 — Channel 2 external capacitor and resistor junction connection
GND 8 — Ground
2 A 9 I Channel 2 falling edge trigger input when 2B = H; Hold low for other input methods
2B 10 I Channel 2 rising edge trigger input when 2 A = L; Hold high for other input methods
2 CLR 11 I Channel 2 rising edge trigger when 2 A = L and 2B = H; Hold high for other input methods; Can cut pulse length short by driving low during output
2 Q 12 O Channel 2 inverted output
1Q 13 O Channel 1 output
1Cext 14 — Channel 1 external capacitor negative connection
1Rext/Cext 15 — Channel 1 external capacitor and resistor junction connection
VCC 16 — Power supply
  1. I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power