Between the first start and the final stop condition, the controller sends bytes of data to the target. The bytes of data can be sent to the target in the following order: target byte address, command byte, then data byte (assuming the target device has multiple registers). Data sent to the target in a different order can cause NACKs to occur. To prevent this, use an oscilloscope to verify that data is being sent to the target device in the correct order (target byte address, command byte, data byte). Remember that clock pulses on the SCL signal line are used to segment off the individual bits being sent on the SDA line. Every frame needs to have 8 clock pulses for the data bits and 1 clock pulse for the ACK or NACK bit.

Figure 3-4 Example of I2C Write Format With Multiple Register Addresses