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Product details

Parameters

Features Enable Pin Frequency (Max) (kHz) 400 VCCA (Min) (V) 1.2 VCCA (Max) (V) 3.3 VCCB (Min) (V) 1.8 VCCB (Max) (V) 5.5 Supply restrictions VCCA <= VCCB Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other I2C level shifters, buffers & hubs

Package | Pins | Size

DSBGA (YZT) 8 2 mm² .928 x 1.928 SSOP (DCT) 8 12 mm² 2.95 x 4 VSSOP (DCU) 8 6 mm² 2 x 3.1 X2SON (DQE) 8 1 mm² 1.4 x 1 open-in-new Find other I2C level shifters, buffers & hubs

Features

  • 2-Bit bidirectional translator for SDA and SCL lines in mixed-mode I2C Applications
  • I2C and SMBus Compatible
  • Less than 1.5-ns Maximum Propagation Delay to Accommodate Standard-mode and Fast-mode I2C Devices and Multiple Masters
  • Allows Voltage-level Translation Between
    • 1.2-V VREF1 and 1.8-V, 2.5-V, 3.3-V,
      or 5-V VREF2
    • 1.8-V VREF1 and 2.5-V, 3.3-V, or 5-V VREF2
    • 2.5-V VREF1 and 3.3-V or 5-V VREF2
    • 3.3-V VREF1 and 5-V VREF2
  • Provides Bidirectional Voltage Translation with no Direction Pin
  • Low 3.5-Ω ON-state Resistance Between Input and Output Ports Provides Less Signal Distortion
  • Open-drain I2C I/O ports (SCL1, SDA1, SCL2, and SDA2)
  • 5-V Tolerant I2C I/O Ports to Support Mixed-mode Signal Operation
  • High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = Low
  • Lockup-free Operation for Isolation when EN = Low
  • Flow-through Pinout for Ease of Printed-circuit-board Trace Routing
  • Latch-up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

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Description

The PCA9306 device is a dual bidirectional I2C and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.2-V to 3.3-V VREF1 and 1.8-V to 5.5-V VREF2.

The PCA9306 device allows bidirectional voltage translations between 1.2 V and 5 V, without the use of a direction pin. The low ON-state resistance (RON) of the switch allows connections to be made with minimal propagation delay. When EN is high, the translator switch is ON, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O, respectively, allowing bidirectional data flow between ports. When EN is low, the translator switch is off, and a high-impedance state exists between ports.

In addition to voltage translation, the PCA9306 device can be used to isolate a 400-kHz bus from a 100-kHz bus by controlling the EN pin to disconnect the slower bus during fast-mode communication.

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Technical documentation

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Type Title Date
* Datasheet PCA9306 Dual Bidirectional I2C Bus and SMBus Voltage-Level Translator datasheet (Rev. M) Apr. 04, 2019
User guides PCA9306 I2C Buffer Evaluation Module Oct. 26, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Technical articles Intro to I2C: what the Internet doesn’t tell you Nov. 24, 2016
Application notes Choosing the Correct I2C Device for New Designs Sep. 07, 2016
Selection guides I2C Infographic Flyer Dec. 03, 2015
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Understanding the I2C Bus Jun. 30, 2015
Application notes Maximum Clock Frequency of I2C Bus Using Repeaters May 15, 2015
Application notes I2C Bus Pull-Up Resistor Calculation Feb. 13, 2015
Application notes Programming Fun Lights With TI's TCA6507 Nov. 30, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$49.00
Description
This EVM can be used to evaluate the PCA9306 product in the DCU package. The I2C buses are easily accessed via SDA_1, SCL_1, SDA_2, and SCL_2 test points, and symmetrically laid out for optimal performance. All IC signals are available through test point connections.
Features
  • Access to VDPU1, VDPU2, EN, SDA1, SCL1, SDA2, and SCL2 pins
  • Footprint for a socket for evaluating multiple PCA9306 devices
  • Footprints to test different capacitive loads
  • Footprints to test different pullup resistor values
  • Different load options allow for the testing of different translator configurations (...)

Design tools & simulation

SIMULATION MODELS Download
SCEJ212A.ZIP (81 KB) - HSpice Model
SIMULATION MODELS Download
SCPM002A.ZIP (54 KB) - IBIS Model
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide
DESIGN TOOLS Download
I2C designer tool
I2C-DESIGNER — Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard with (...)
Features
  • GUI-based web application
  • Exportable designs
  • JSON file uploader
  • Bill of materials generator

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CAD/CAE symbols

Package Pins Download
DSBGA (YZT) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options
X2SON (DQE) 8 View options

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