SCPS295A September   2024  – July 2025 TPLD801

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT macro-cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop/Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch with Set/Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-Cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter/Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Edge Detector Mode
        3. 7.3.4.3 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-Cell
      6. 7.3.6 Selectable Frequency Oscillator
        1. 7.3.6.1 Oscillator Power Modes
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
        1. 7.4.1.1 GPIO Quick Charge
        2. 7.4.1.2 Initialization
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST CONDITIONS VCC MIN TYP MAX UNIT
Digital IO
tpd Delay Digital input Push-pull output Rising 1.8V ± 0.15V 46.9 ns
Falling 39.5
Rising 3.3V ± 0.3V 27.3
Falling 26.4
Rising 5V ± 0.5V 22.3
Falling 22.5
tpd Delay Digital input with Schmitt trigger Push-pull output Rising 1.8V ± 0.15V 50.8 ns
Falling 42.2
Rising 3.3V ± 0.3V 29.7
Falling 27.2
Rising 5V ± 0.5V 24.2
Falling 22.8
tpd Delay Low-voltage digital input Push-pull output Rising 1.8V ± 0.15V 45.6 ns
Falling 49.5
Rising 3.3V ± 0.3V 25.4
Falling 33.0
Rising 5V ± 0.5V 19.6
Falling 31.5
tpd Delay Digital input Open-drain NMOS output Rising 1.8V ± 0.15V ns
Falling 39.3
Rising 3.3V ± 0.3V
Falling 26.2
Rising 5V ± 0.5V
Falling 22.3
tpd Delay Output enable from pin OE Push-pull output Hi-Z to 1 1.8V ± 0.15V 45.9 ns
3.3V ± 0.3V 27.3
5V ± 0.5V 22.4
Hi-Z to 0 1.8V ± 0.15V 41.1
3.3V ± 0.3V 24.5
5V ± 0.5V 19.6
Configurable Use Logic
tpd Delay 2-bit LUT IN OUT Rising 1.8V ± 0.15V 1.16 ns
Falling 1.31
Rising 3.3V ± 0.3V 1.16
Falling 1.31
Rising 5V ± 0.5V 1.16
Falling 1.31
tpd Delay 3-bit LUT IN OUT Rising 1.8V ± 0.15V 1.04 ns
Falling 1.26
Rising 3.3V ± 0.3V 1.04
Falling 1.26
Rising 5V ± 0.5V 1.04
Falling 1.26
tpd Delay 4-bit LUT IN OUT Rising 1.8V ± 0.15V 1.62 ns
Falling 1.99
Rising 3.3V ± 0.3V 1.62
Falling 1.99
Rising 5V ± 0.5V 1.62
Falling 1.99
tpd Delay DFF/Latch CLK Q Rising 1.8V ± 0.15V 1.32 ns
Falling 1.34
Rising 3.3V ± 0.3V 1.32
Falling 1.34
Rising 5V ± 0.5V 1.32
Falling 1.34
tpd Delay DFF/Latch nRST/nSET Q Rising 1.8V ± 0.15V 1.43 ns
Falling 1.46
Rising 3.3V ± 0.3V 1.43
Falling 1.46
Rising 5V ± 0.5V 1.43
Falling 1.46
Counter/Delay
tpd Delay Counter - Delay mode Rising edge of IN Rising edge of OUT Falling edge triggered 1.8V ± 0.15V 2.61 ns
Falling edge of IN Falling edge of OUT Rising edge triggered 2.59
Rising edge of IN Rising edge of OUT Falling edge triggered 3.3V ± 0.3V 2.61
Falling edge of IN Falling edge of OUT Rising edge triggered 2.59
Rising edge of IN Rising edge of OUT Falling edge triggered 5V ± 0.5V 2.61
Falling edge of IN Falling edge of OUT Rising edge triggered 2.59
Oscillator
ferr Oscillator frequency error OSC025 kHz 1.8V ± 0.15V -5 5 %
3.3V ± 0.3V -5 5
5V ± 0.5V -5 5
OSC0 2MHz 1.8V ± 0.15V -5 5 %
3.3V ± 0.3V -5 5
5V ± 0.5V -5 5
td_osc Oscillator startup delay OSC025 kHz 1.8V ± 0.15V 14.3 µs
3.3V ± 0.3V 14.2
5V ± 0.5V 14.1
OSC0 2MHz 1.8V ± 0.15V 6.24 µs
3.3V ± 0.3V 6.43
5V ± 0.5V 6.64
tset_osc Oscillator startup settling time OSC025 kHz 1.8V ± 0.15V 1 µs
3.3V ± 0.3V 1
5V ± 0.5V 1
OSC0 2MHz 1.8V ± 0.15V 7 µs
3.3V ± 0.3V 7
5V ± 0.5V 7
td_err Delay error OSC (Forced power on) 1.71V to 5.5V 0 1 CLK cycle
Programmable Filter
tpflt_pw Pulse width Programmable filter - Edge detect mode Rising edge of OUT Falling edge of OUT 1 cell 1.8V ± 0.15V 138.0 ns
3.3V ± 0.3V 141.3
5V ± 0.5V 141.7
2 cells 1.8V ± 0.15V 232.6 ns
3.3V ± 0.3V 236.0
5V ± 0.5V 236.5
3 cells 1.8V ± 0.15V 326.8 ns
3.3V ± 0.3V 330.5
5V ± 0.5V 330.9
4 cells 1.8V ± 0.15V 420.9 ns
3.3V ± 0.3V 424.7
5V ± 0.5V 425.0
tpflt_pd Delay Programmable filter - Edge detect mode Any cells 1.8V ± 0.15V 24.7 ns
3.3V ± 0.3V 21.8
5V ± 0.5V 21.6
tpflt_d Delay Programmable filter - Both edge delay mode Rising/Falling edge of IN Rising/Falling edge of OUT 1 cell 1.8V ± 0.15V 208.4 ns
3.3V ± 0.3V 191.5
5V ± 0.5V 186.9
2 cells 1.8V ± 0.15V 303.3 ns
3.3V ± 0.3V 286.3
5V ± 0.5V 281.5
3 cells 1.8V ± 0.15V 397.7 ns
3.3V ± 0.3V 380.6
5V ± 0.5V 375.9
4 cells 1.8V ± 0.15V 491.9 ns
3.3V ± 0.3V 474.6
5V ± 0.5V 469.8