SCPS309B August   2025  – June 2026 TXE8116

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8116 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TXE8116 TXE8116 DGS (VSSOP) Package, 24-Pin (Top View)Figure 4-1 TXE8116 DGS (VSSOP) Package, 24-Pin (Top View)
TXE8116 TXE8116 RGE (VQFN) Package, 24-Pin (Top View)Figure 4-2 TXE8116 RGE (VQFN) Package, 24-Pin (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME DGS
(VSSOP24)		 RGE
(VQFN)
P1.7 13 4 I/O P-port input/output. At power on, Port 1 - IO #7 is configured as an input
P1.6 14 5 I/O P-port input/output. At power on, Port 1 - IO #6 is configured as an input
P1.5 15 6 I/O P-port input/output. At power on, Port 1 - IO #5 is configured as an input
P1.4 16 7 I/O P-port input/output. At power on, Port 1 - IO #4 is configured as an input
P1.3 17 8 I/O P-port input/output. At power on, Port 1 - IO #3 is configured as an input
P1.2 18 9 I/O P-port input/output. At power on, Port 1 - IO #2 is configured as an input
P1.1 19 10 I/O P-port input/output. At power on, Port 1 - IO #1 is configured as an input
P1.0 20 11 I/O P-port input/output. At power on, Port 1 - IO #0 is configured as an input
CS 21 12 I SPI chip select input. Internal pull-up resistor
SCLK 22 13 I SPI serial clock input. Internal pull-down resistor
SDI 23 14 I SPI serial data input.
RESET/FAIL-SAFE 24 15 I Active Low reset or fail-safe input. An external pull-up resistor connects to VCC.
INT 1 16 O Open-Drain Interrupt output. An external pull-up resistor connects to VCC.
SDO 2 17 O SPI serial data output. Push-pull output
VCC 3 18 P Supply voltage
GND 4 19 G Ground
P0.0 5 20 I/O P-port input/output. At power on, Port 0 - IO #0 is configured as an input
P0.1 6 21 I/O P-port input/output. At power on, Port 0 - IO #1 is configured as an input
P0.2 7 22 I/O P-port input/output. At power on, Port 0 - IO #2 is configured as an input
P0.3 8 23 I/O P-port input/output. At power on, Port 0 - IO #3 is configured as an input
P0.4 9 24 I/O P-port input/output. At power on, Port 0 - IO #4 is configured as an input
P0.5 10 1 I/O P-port input/output. At power on, Port 0 - IO #5 is configured as an input
P0.6 11 2 I/O P-port input/output . At power on, Port 0 - IO #6 is configured as an input
P0.7 12 3 I/O P-port input/output. At power on, Port 0 - IO #7 is configured as an input
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power