SCPS309B August   2025  – June 2026 TXE8116

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 SPI Bus Timing Requirements
    8. 5.8 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 I/O Port
      2. 7.3.2 Interrupt Output (INT)
      3. 7.3.3 Reset Input (RESET)
      4. 7.3.4 Bus Hold
      5. 7.3.5 Fail-safe Mode
      6. 7.3.6 Software Reset Call
      7. 7.3.7 Daisy Chain
      8. 7.3.8 Multi Port
      9. 7.3.9 Feature Register Mapping
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 SPI Data Format
      3. 7.5.3 Burst Mode
      4. 7.5.4 SPI Write
      5. 7.5.5 SPI Read
      6. 7.5.6 SPI Daisy Chain
    6. 7.6 TXE8116 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-On Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2 Interrupt Output (INT)

The TXE8116 devices generate an interrupt on any rising or falling edge of an input I/O, provided that the interrupt for that I/O is not masked. When an input pin state is different than the input read register state, the corresponding interrupt flag bit is set, and the INT output is asserted. The INT pin is open-drain and requires an external pullup resistor to VCC use the interrupt feature, otherwise this pin can be left floating.

I/Os configured as outputs do not generate interrupts. Switching a pin from output to input can generate a fault interrupt if the actual pin level does not match the stored input port register value. If an I/O port is previously in input state and detected an interrupt as switching to output, this action does not clear the interrupt flag. This action only masks the interrupt pin. Then when the port is reconfigured as input, the interrupt comes back.

With the following conditions, the interrupt status bits can be cleared and the INT pin deasserted.

  • Hardware reset from RESET pin - this deasserts the interrupt temporarily as POR is going to assert the interrupt
  • Entering fail-safe mode - this mode disables and de-assert the interrupt
  • Reading Interrupt Flag Status Register
  • Setting the corresponding bit as 1 in Interrupt Mask Register

There are four sources of interrupts in TXE8116:

  1. Smart Input Pin Interrupt: Smart Interrupt is enabled or disabled at I/O port level by setting the corresponding port bit in the Smart Interrupt Register. If Smart Interrupt (the corresponding register bit as 0) is enabled and an interrupt is generated, the interrupt clears if the I/O state goes back to the initial logic state or the interrupt reads the Interrupt Flag Status Register. Refer to Table 7-1 for the different interrupt clearing scenarios. To avoid missing the interrupt clear due to false IO toggle, TI strongly recommends to enable the glitch filter enable in the Input Glitch Filter Enable Register.
  2. Regular Input Pin Interrupt: When Smart Interrupt is disabled (the corresponding register bit as 1) in the Smart Interrupt Register, the I/O state going back to the initial logic state cannot clear the interrupt, only reading the Interrupt Flag Status Register clears the interrupt.
    Table 7-1 Interrupt Flag Clearing Scenarios for Smart Interrupt
    SMART INTERRUPT CS STATE WHEN IO INPUT CHANGES INTERRUPT FLAG CLEARS
    Disable CS = High CS to be low and SPI reading Interrupt Flag Status Register
    Disable CS = Low Reading Interrupt Flag Status Register
    Enable CS = High
    1. IO state going back to the initial state.
    2. CS to be low and SPI reading Interrupt Flag Status Register.
    Enable CS = Low
    1. IO states going back to the initial state shall automatically clear the interrupt flag at least 30ns after CS becomes high.
    2. Reading Interrupt Flag Status Register.
  3. POR Interrupt : the POR fault bit is set in the Fault Status Register for each POR recovery, which also generates an interrupt. The interrupt is only cleared when the Fault Status Register is read.
  4. Fail-safe Redundancy Failure Interrupt: When the fail-safe redundancy check is enabled, and if any fail-safe redundancy check failure occurs, a fail-safe sync fault bit is set in the Fault Status Register. This action also generates an interrupt. The interrupt is only cleared when the Fault Status Register is read.

Interrupt Masking

Interrupts from all input I/Os are unmasked by default. To mask an interrupt, the corresponding I/O bit needs to be set in the interrupt mask register. The interrupt generated by POR recovery cannot be masked.

If the state of an input I/O is changed and the corresponding bit in the Interrupt mask register is set to 1, the interrupt is masked and the INT pin is not asserted. The corresponding bit in the interrupt flag status register also stays at 0 and is blocked by the interrupt mask bit.

The interrupts generated by fail-safe redundancy check fail is disabled if the fail-safe redundancy check enable bit is 0.

Multiple ports can be configured for interrupt masking at the same time by using multi-port command.