SDAA040 July   2025 MSPM0C1104

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 PWM Signal Capture Introduction
    2. 1.2 MSPM0C110x Introduction
  5. 2PWM Signal Capture
    1. 2.1 PWM Signal Capture Methods
    2. 2.2 PWM Signal Capture with TIMx CC Block
    3. 2.3 PWM Signal Capture with GPIO Interrupt
    4. 2.4 Comparison of Different PWM Signal Capture Design
  6. 3Software Realization
    1. 3.1 Identifying Rising and Falling Edge
    2. 3.2 Time Order Classification
    3. 3.3 Signal Filter and Result Calculation
  7. 4System Test
    1. 4.1 Test Setup
    2. 4.2 Variable Monitor
    3. 4.3 PWM Signal Capture Resolution Test and Comparison
  8. 5Summary
  9. 6References

3.2 Time Order Classification

This demo takes the GPIO falling edge as the start of one PWM pulse. The correct time order must be: the first falling edge is detected, the rising edge is detected and the second falling edge is detected. In some corner cases, the PWM duty cycle is less than 0.2% or the PWM duty cycle is larger than 99.7%. The time order can be inaccurate due to the noise. The gflag and gflag_2 in the demo are set to identify the correct time order. The corresponding actions in different situations are listed in Table 3-2

Software Diagram of PWM Duty and Period Capture with GPIO Interrupt Figure 3-1 Software Diagram of PWM Duty and Period Capture with GPIO Interrupt
Table 3-2 Actions in GPIO Interrupt Handler in Different Conditions
GPIO Edge gflag gflag_2 Actions
Rising edge 0 0 Do nothing
0 1 Does not occur
1 0 Record COUNTERREGS.CTR to DUTY, Set gflag_2
1 1 Reset counter and flags
Falling edge 0 0 Start Timer, set gflag
0 1 Does not occur
1 0 Reset counter and flags
1 1 Record COUNTERREGS.CTR to PRD, Reset flags