For noise rejection benchmarking, the test uses the following configuration.

• The VREF is shared with 16-bit SAR ADC in TMS320F28P650 MCU and AMC0330R device as shown in Figure 2-2
• The AWG injects a modulated reference voltage, with VREF(NOM) = 3V and VREF(INJ) = 300mVpp (sinewave) (Figure 2-4)
• The input voltage is zero (VIN=0V)

Figure 2-4 Waveform Applied to V_REF for the Rejection Test

Test procedure is as follows:

• The AWG sweeps V_REF from 500Hz to 100kHz in multiple steps
• At every step, the MCU stores 8192 ADC samples
• At every step, the software in personal computer (PC) applies Fast Fourier Transformation (FFT) at the ADC samples and reads the peak value at the frequency corresponding to the step and AWG output
• The software calculates peak amplitude V_ADC(OUT) from the FFT peak value
• System calculates the attenuation

Figure 2-5 shows the plot for all steps in the range from 500Hz to 100Hz.

Figure 2-5 Ratiometric Configuration V_REF Noise Rejection