Voltage transients were applied to input as well to check the robustness of the converter with respect to line disturbances: a line step between 14V and 20V is applied, and the output voltage ripple is observed. Results are shown in Figure 4-8 and Figure 4-9 for configurations 'Resistor' and 'Analog', respectively. The compensation loop used leads to a phase margin of 68⁰, which makes the device stable. Compared to the load transient analysis, the overshoot is causing the device to stop switching for a shorter time interval here (tens of µs), while the overshoot magnitude is comparable if not greater: this is because of how fast the device is in regulating the output voltage, this time interval is shorter than the propagation along the signal path that senses the output voltage and goes through the FB pin.

Figure 4-8 Line Transient for Configuration Resistor (24Vout)

Figure 4-9 Line Transient for Configuration Analog (48Vout)