SDAA249 January   2026 AMC3330-Q1 , INA148-Q1 , TPS61170-Q1 , TPSI2240-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Background
    2. 1.2 Operation Principle
  5. 2Hardware Design
    1. 2.1 Solid State Relay (SSR)
    2. 2.2 Resistors
      1. 2.2.1 Minimum Resistance
      2. 2.2.2 Maximum Resistance
      3. 2.2.3 Resistance Ratio
    3. 2.3 Bias Supply
    4. 2.4 Amplifier
      1. 2.4.1 MCU on the Low Voltage Side
      2. 2.4.2 MCU on the AC Side
  6. 3Software Design
    1. 3.1 Settling Time
    2. 3.2 SSR Sequence
    3. 3.3 Voltage Threshold
    4. 3.4 Moving Average
    5. 3.5 Plausibility Check
    6. 3.6 Control Scheme Summary
  7. 4Simulation Results
    1. 4.1 Settling Time
    2. 4.2 Input Voltage Range
    3. 4.3 Plausibility Check
    4. 4.4 Accuracy
    5. 4.5 Influence of the Y Capacitor
  8. 5Summary
  9. 6References

2.3 Bias Supply

From the equivalent circuit in Figure 1-2, the system resistance can be calculated by the sensed voltage Vin(DC), as described in Equation 1 and Equation 2. The value of the bias power supply mainly affects the resolution of the ADC reading in insulation monitoring. When no insulation failure occurs, Riso_NOR is at a level above 10MΩ; Riso_NOR is greater than Rin. The system-equivalent resistance and the sensed voltage can be expressed as:

Equation 17. R s y s N O R = 0.5 × R s t + 0.5 × R i s o N O R
Equation 18. V i n D C N O R = R i n R s y s N O R + R i n × V D C ≅ 2 × R i n R s t + R i s o N O R × V D C

When a single insulation failure occurs at either the line or neutral, and Riso is reduced to the insulation failure threshold of 110kΩ; RisoFLT is less than Riso_NOR. The system-equivalent resistance and the sensed voltage can be expressed as:

Equation 19. R s y s F L T ≅ 0.5 × R s t + R i s o F L T
Equation 20. V i n D C F L T = R i n R s y s F L T + R i n × V D C ≅ R i n 0.5 × R s t + R i s o F L T × V D C

Therefore, under conditions of insulation failure and normal conditions, the difference of the sensed voltage can be expressed as:

Equation 21. ∆ V i n D C = V i n D C F L T - V i n D C N O R = R i n × V D C × 1 0.5 × R s t + R i s o F L T - 2 R s t + R i s o N O R

To achieve the highest resolution in insulation monitoring, the difference in sensed voltage between the fault conditions and normal conditions must be maximized, meaning, ΔVin(DC) must be maximized.

According to the previous analysis, the smaller the switch in resistance value, the less the switch affects the accuracy of the Y capacitor. According to Equation 13, when VAC is 310V, assuming the total equivalent switch-in resistance is at the minimum value to improve accuracy, the Rin and Rst values at different values of VDC can be calculated, as summarized in Table 2-2.

Table 2-2 Switch-In Resistance Values in Different DC Bias Voltages
VDC 1 / r Rin Rst ΔVin(DC)
(Asymmetric insulation failure from Riso_NOR = 10MΩ to Riso_FLT = 110kΩ)
12V 194.2 8.2kΩ 1585kΩ 92mV
24V 201.4 7.9kΩ 1584kΩ 177mV
40V 211.1 7.5kΩ 1580kΩ 282mV
80V 236.0 6.7kΩ 1574kΩ 505mV

For the same VDC, Table 2-2 shows the minimum value of 1 / r, that is the maximum value of Rin. If 1 / r continues to decrease, the sensed voltage range exceeds 3.3V.

According to Table 2-2, under different values of VDC, the value of Rst is almost the same, while the larger the VDC, the greater the value of VDC × Rin. According to Equation 21, the higher the VDC, the higher the ΔVin(DC), allowing insulation failures to be distinguished more effectively from normal conditions.

Due to the safety requirements of the low-voltage system, the voltage on the low-voltage side cannot be too high, so 40V is ultimately chosen as the DC bias supply voltage. If the low-voltage battery is rated for 48V, this DC bias supply voltage can be derived directly from the low-voltage battery. If the low-voltage battery is rated for 12V, a boost circuit is usually needed to generate 40 volts.

The peak transient current provided by this DC power supply is shown as:

Equation 22. I p e a k = V D C 0.5 × R s t + R i n

According to the parameters of a 40V value of VDC in Table 2-2, the calculated Ipeak is less than 1mA, so the IMD circuit does not have high requirements for the current capacity of the VDC.

The bias power of an OBC and HVLV DC-DC system usually includes a flyback converter. The simplest way to generate the 40V VDC is to leverage the flyback topology by implementing one extra winding, and the LM5155-Q1 device is a common type of flyback controller in OBC bias supply. More details on bias supply architectures can be found in the references section [3] and [4]. Considering the cross-regulation of flyback, the output of the winding needs an LDO or a dump load.

Another implementation method is through the boost converter. The TPS61170‑Q1 boost converter offered by TI operates at 1.2MHz, can deliver up to 38V, and maintains good efficiency even at light loads; making the device a potential option for generating a stable VDC for the IMD circuit. More details on this component can be found in the references section [3] and [5].

A charge pump can also be used for generating VDC and can be implemented by the TLC555-Q1 device. Since the square-wave output switches between the supply voltage and GND, with few additional capacitors and diodes, this makes the TLC555-Q1 device appropriate for generating a voltage multiplier. More details on how to boost voltage using the TLC555-Q1 device can be found in the reference section [6].