SDAA344 August   2026 AM263P4

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Purpose and Scope
    2. 1.2 EOS Definition and Importance
    3. 1.3 EOS vs ESD
  5. 2 Device Overview and EOS Susceptibility
    1. 2.1 AM26xx Series Overview
    2. 2.2 C2000 Series Overview
    3. 2.3 Critical Pins and Interfaces
      1. 2.3.1 Power Supply Pins
      2. 2.3.2 Reset and Configuration Pins:
      3. 2.3.3 Communication Interface Pins:
      4. 2.3.4 Analog Input Pins (ADC):
      5. 2.3.5 PWM Output Pins (C2000):
    4. 2.4 Power Domains and Sequencing Requirements
      1. 2.4.1 AM26xx Power Domains:
      2. 2.4.2 Sequencing requirements:
      3. 2.4.3 C2000 Power Domains:
      4. 2.4.4 Consequences of Sequencing Violations:
  6. 3 EOS Fundamentals and Failure Mechanisms
    1. 3.1 ESD Diode Current Specification
      1. 3.1.1 Understanding the Specification
      2. 3.1.2 ESD Diode Protection Structure
      3. 3.1.3 Important Side Effects During Power Cycling
    2. 3.2 System Design EOS Sources
      1. 3.2.1 Bus Contention
      2. 3.2.2 Incorrect Voltage Levels
      3. 3.2.3 Impedance Mismatch and Signal Integrity
      4. 3.2.4 Inadequate Filtering and Grounding
  7. 4 I/O Interface Protection
    1. 4.1 Digital I/O Protection
    2. 4.2 Communication Interface Protection
      1. 4.2.1 Industrial Ethernet (AM26xx RMII/RGMII):
      2. 4.2.2 CAN Bus:
      3. 4.2.3 SPI, I2C, UART:
    3. 4.3 PWM Output Protection (C2000)
  8. 5 PCB Design Guidelines
    1. 5.1 Component Placement
    2. 5.2 Routing
    3. 5.3 Ground Plane Design
    4. 5.4 EOS-Specific Layout Considerations
    5. 5.5 Manufacturing and Assembly EOS Prevention
      1. 5.5.1 Board Assembly EOS Sources
      2. 5.5.2 What to Look For During Manufacturing
  9. 6 In-Circuit Test (ICT) EOS Mitigation
    1. 6.1 Hot-Plugging Risks
      1. 6.1.1 Hot-Plugging Failure Mechanisms
      2. 6.1.2 Hot-Plugging Prevention
    2. 6.2 Power Sequencing During ICT
      1. 6.2.1 Key Sequencing Requirements
      2. 6.2.2 ICT Power Sequencing Violations
    3. 6.3 Charged Board Events (CBE)
      1. 6.3.1 CBE Mechanism
      2. 6.3.2 Mitigating High-Capacitance Charge Dissipation
        1. 6.3.2.1 Reverse Charging Mechanism
        2. 6.3.2.2 Board-Level Shunt Protection
    4. 6.4 VSS-First Connection Strategy
      1. 6.4.1 VSS-First Design Principle
      2. 6.4.2 Implementation Methods
    5. 6.5 Manual Connector Protection
      1. 6.5.1 Protection Techniques
  10. 7 External Protection Components
    1. 7.1 TVS Diode Selection
      1. 7.1.1 Key Parameters:
      2. 7.1.2 Unidirectional vs Bidirectional Usage:
      3. 7.1.3 Placement:
    2. 7.2 Filter Design
    3. 7.3 Voltage Clamping Solutions
  11. 8 Design Examples and Case Studies
    1. 8.1 Case Study: Insufficient VDD/VSS Plane Connections
    2. 8.2 Case Study: Invalid PORz Sequencing Causing I/O Buffer Shoot-Through
    3. 8.3 Case Study: Isolator Output Enable Causing Signal Before Valid Reset
    4. 8.4 Case Study: Manufacturing Test Process Improvements
  12. 9 Summary and Recommendations
    1. 9.1 Key Takeaways
    2. 9.2 Design Checklist for AM26xx/C2000 Systems
  13. 10References

6.3.2 Mitigating High-Capacitance Charge Dissipation

High-capacitance nodes, such as power supply networks (VDD3V3) present a Charged Board Event (CBE) risk due to their capacity to store and discharge significant energy.