SDAA352 May   2026 TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Architecture
    1. 2.1 Core Configuration
    2. 2.2 Power Domain Architecture
    3. 2.3 IPC Framework Overview
  6. 3Heartbeat Monitoring Design
    1. 3.1 Ping-Pong Protocol
    2. 3.2 Dual-Task Architecture
    3. 3.3 Crash Detection Logic
  7. 4 Recovery Mechanism
    1. 4.1 Power State Transitions
  8. 5 Implementation Details
    1. 5.1 Configuration Parameters
    2. 5.2 Parameter Tuning Guidance:
    3. 5.3 Linux-Side rpmsg_char Implementation
  9. 6 Test Results and Performance
    1. 6.1 Timing Profile
    2. 6.2 Recovery Verification
  10. 7Summary
  11. 8References

2.1 Core Configuration

The TDA4x SoC contains multiple processing cores organized into clusters. Table 2-1 lists the core configuration used in this implementation.

Table 2-1 Core Configuration
Core Type Operating System Role
MCU1_0 R5F FreeRTOS LPM Driver + Heartbeat Monitor
MCU1_1 R5F FreeRTOS Not used in this configuration
MCU2_0 R5F FreeRTOS Remote core (monitored)
MCU2_1 R5F FreeRTOS Remote core (monitored)
MCU3_0 R5F FreeRTOS Remote core (monitored)
MCU3_1 R5F FreeRTOS Remote core (monitored)
MPU1_0 A72 Linux Linux core (monitored)
C7x_1 DSP FreeRTOS DSP core (monitored)

The MCU1_0 core is designated as the heartbeat monitor because the core resides in the MCU domain, which remains powered during MCU Only Mode. This allows the monitor to survive MAIN domain power cycles and orchestrate recovery.