Product details

Arm CPU 2 Arm Cortex-A72 Arm MHz (Max.) 2000 Co-processor(s) MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 4 Arm Cortex-R5F (lockstep opt) CPU 64-bit Graphics acceleration 1 3D Display type 2 DPI, 1 DSI, 1 EDP Protocols Ethernet Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 Deep Learning accelerator, 1 Depth and Motion accelerator, 1 Video Encode/Decode accelerator, 1 Vision Processing accelerator Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1, LP8764-Q1 Operating temperature range (C) -40 to 125
Arm CPU 2 Arm Cortex-A72 Arm MHz (Max.) 2000 Co-processor(s) MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 4 Arm Cortex-R5F (lockstep opt) CPU 64-bit Graphics acceleration 1 3D Display type 2 DPI, 1 DSI, 1 EDP Protocols Ethernet Ethernet MAC 8-Port 2.5Gb switch PCIe 4 PCIe Gen 3 switch Hardware accelerators 1 Deep Learning accelerator, 1 Depth and Motion accelerator, 1 Video Encode/Decode accelerator, 1 Vision Processing accelerator Features Vision Analytics Operating system Linux, QNX, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1, LP8764-Q1 Operating temperature range (C) -40 to 125
FCBGA (ALF) 827 576 mm² 24 x 24 FCBGA (ALF) 827

Processor cores:

  • C7x floating point, vector DSP, up to 1.0 GHz, 80 GFLOPS, 256 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Six Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four Arm Cortex-R5F MCUs in general compute partition
  • Two C66x floating point DSP, up to 1.35 GHz, 40 GFLOPS, 160 GOPS
  • 3D GPU PowerVR Rogue 8XE GE8430, up to 750 MHz, 96 GFLOPS, 6 Gpix/sec
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 3733 MT/s
    • 32-bit data bus with inline ECC up to 14.9GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1
  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting (total of 8 external ports)
    • Up to eight 2.5Gb SGMII
    • Up to eight RMII (10/100) or RGMII (10/100/1000)
    • Up to two QSGMII
  • Up to four PCI-Express (PCIe) Gen3 controllers
    • Up to two lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Two USB 3.0 dual-role device (DRD) subsystem
    • Two enhanced SuperSpeed Gen1 Ports
    • Each port supports Type-C switching
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    Automotive interfaces:

  • Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Two CSI2.0 4L RX plus One CSI2.0 4L TX
    • 2.5Gbps RX throughput per lane (20Gbps total)

    Display subsystem:

  • One eDP/DP interface with Multi-Display Support (MST)
    • HDCP1.4/HDCP2.2 high-bandwidth digital content protection
  • One DSI TX (up to 2.5K)
  • Up to two DPI

    Audio interfaces:

  • Twelve Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
  • Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
  • Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI and one QSPI flash interfaces
    • or one HyperBus™ and one QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • C7x floating point, vector DSP, up to 1.0 GHz, 80 GFLOPS, 256 GOPS
  • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 1MB shared L2 cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Six Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Four Arm Cortex-R5F MCUs in general compute partition
  • Two C66x floating point DSP, up to 1.35 GHz, 40 GFLOPS, 160 GOPS
  • 3D GPU PowerVR Rogue 8XE GE8430, up to 750 MHz, 96 GFLOPS, 6 Gpix/sec
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 3733 MT/s
    • 32-bit data bus with inline ECC up to 14.9GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1
  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting (total of 8 external ports)
    • Up to eight 2.5Gb SGMII
    • Up to eight RMII (10/100) or RGMII (10/100/1000)
    • Up to two QSGMII
  • Up to four PCI-Express (PCIe) Gen3 controllers
    • Up to two lanes per controller
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Two USB 3.0 dual-role device (DRD) subsystem
    • Two enhanced SuperSpeed Gen1 Ports
    • Each port supports Type-C switching
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    Automotive interfaces:

  • Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Two CSI2.0 4L RX plus One CSI2.0 4L TX
    • 2.5Gbps RX throughput per lane (20Gbps total)

    Display subsystem:

  • One eDP/DP interface with Multi-Display Support (MST)
    • HDCP1.4/HDCP2.2 high-bandwidth digital content protection
  • One DSI TX (up to 2.5K)
  • Up to two DPI

    Audio interfaces:

  • Twelve Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
  • Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
  • Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI and one QSPI flash interfaces
    • or one HyperBus™ and one QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The TDA4VM processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VM devices a great fit for several industrial applications, such as: Robotics, Machine Vision, Radar, and so on. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate dual core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to six Arm Cortex-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm Cortex-A72’s unencumbered for applications. The integrated “8XE GE8430” GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VM processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VM devices a great fit for several industrial applications, such as: Robotics, Machine Vision, Radar, and so on. The TDA4VM provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new “MMA” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate dual core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to six Arm Cortex-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm Cortex-A72’s unencumbered for applications. The integrated “8XE GE8430” GPU offers up to 100 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VM family also includes an MCU island eliminating the need for an external system microcontroller.

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Technical documentation

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Type Title Date
* Data sheet TDA4VM Jacinto™ Processors for ADAS and Autonomous Vehicles Silicon Revisions 1.0 and 1.1 datasheet (Rev. J) PDF | HTML 31 Aug 2021
* Errata J721E DRA829/TDA4VM Processors Silicon Revision 1.1/1.0 (Rev. C) PDF | HTML 27 Jul 2022
Functional safety information DRA829_TDA4VM Report on the Safety Certificate - Automotive 07 Dec 2022
Functional safety information DRA829_TDA4VM Report on the Safety Certificate - Industrial 07 Dec 2022
Functional safety information DRA829_TDA4VM Safety Certificate - Automotive 06 Dec 2022
Functional safety information DRA829_TDA4VM Safety Certificate - Industrial 06 Dec 2022
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. D) PDF | HTML 30 Nov 2022
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. B) 19 Jul 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 Apr 2022
Application note Jacinto7 HS Device Development PDF | HTML 13 Jan 2022
User guide C6000-to-C7000 Migration User's Guide (Rev. D) PDF | HTML 10 Jan 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 Jan 2022
White paper Designing an Efficient Edge AI System with Highly Integrated Processors PDF | HTML 10 Dec 2021
Application note Jacinto7 HS Device Flashing Solution PDF | HTML 09 Dec 2021
Functional safety information Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13 Oct 2021
User guide DRA829/TDA4VM Technical Reference Manual (Rev. C) 04 Oct 2021
Application note Performance and power benchmarking with TDA4 Edge AI processors PDF | HTML 01 Sep 2021
Application note TISCI Server Integration in Vector AUTOSAR PDF | HTML 16 Jul 2021
Application note TDA4 Flashing Techniques PDF | HTML 08 Jul 2021
Application note J721E DDR Firewall Example PDF | HTML 01 Jul 2021
Application note Hardware Accelerated Structure From Motion on TDA4VM PDF | HTML 23 Apr 2021
Application note Efficient Visual Localization on TDA4VM (Rev. A) PDF | HTML 19 Apr 2021
Application note TDA4VMid VPAC ISP Tuning Overview (Rev. A) PDF | HTML 14 Jan 2021
White paper Jacinto™ 7 프로세서의 보안 구현 도구 04 Jan 2021
White paper Security Enablers on Jacinto™ 7 Processors 04 Jan 2021
White paper Sicherheitsaktivierung auf Jacinto™ 7-Prozessoren 04 Jan 2021
White paper Differenzierungsmöglichkeit durch MCU-Integration Prozessoren der Reihe Jacinto™ 22 Oct 2020
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22 Oct 2020
White paper Jacinto™ 7 프로세서의 MCU 통합으로 차별화 지원 22 Oct 2020
Application note MMC SW Tuning Algorithm PDF | HTML 18 Aug 2020
Application note OSPI Tuning Procedure PDF | HTML 08 Jul 2020
White paper 360度環景系統與自動停車系統 01 Mar 2020
White paper 360도 인식이 가능한서라운드뷰와 자동 주차 시스템 01 Mar 2020
White paper 運用 Jacinto™ 7 處理器的汽車設計功能安全特性 01 Mar 2020
White paper 오토모티브 설계 시 Jacinto™ 7 프로세서의 기능적 안전성 활용하기 01 Mar 2020
White paper A 360-degree view of surround-view and automated parking systems 10 Dec 2019
More literature Jacinto 7 EVM Quick Start Guide for TDA4VM and DRA829V Processors 10 Oct 2019
Application note Jacinto 7 High-Speed Interface Layout Guidelines 04 Oct 2019
User guide VCOP Kernel-C to C7000 Migration Tool User's Guide (Rev. C) PDF | HTML 11 Aug 2019
Certificate TÜV NORD Certificate for Functional Safety Software Development Process 03 Feb 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Application software & framework

MOMENTA-3P-DL-ALGORITHMS — Momenta deep learning algorithms for ADAS forward camera applications on TDA4x processors

Momenta’s deep learning based algorithms for ADAS applications make full use of the DSP cores and accelerators on TDA4x for neural network processing. Designed to achieve market leading computational and power efficiency, Momenta’s algorithms offer an array of pre- and post-imaging (...)
From: Momenta
Driver or library

WIND-3P-VXWORKS-LINUX-OS — Wind River Processors VxWorks and Linux operating systems

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
Firmware

VCTR-3P-AUTOSAR — Vector AUTOSAR, HSM, and networking software components for the automotive industry

Vector is the leading manufacturer of software tools and embedded components for the development of electronic systems and networking from CAN to Automotive Ethernet. Vector has been a partner of automotive manufacturers, suppliers and related industries since 1988, providing software components, (...)
IDE, configuration, compiler or debugger

C7000-CGT — C7000 code generation tools - compiler

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)
IDE, configuration, compiler or debugger

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)
Software programming tool

TI-EDGE-AI-CLOUD — Evaluate deep learning inference performance on TDA4x processors

TI Edge AI Cloud is a free online service that lets you evaluate accelerated deep learning inference on TDA4x processors. You do not need to purchase an evaluation board. The service is Python-based; and it only takes a few minutes to login, deploy a model, and get a variety of performance (...)
Design tool

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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FCBGA (ALF) 827 View options

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