CPSW or Common Platform Switch is a TI proprietary HW IP which enables the networking capabilities on the AM26x devices. CPSW subsystem provides IEEE 802.3 standard Ethernet gigabit speed packet communication for the device and can also be configured as an Ethernet switch. CPSW3G supports 10/100/1000 Ethernet ports with selectable MII, RMII, RGMII interfaces. The AM26x devices carry a 3-port Gigabit CPSW3G subsystem. The 3-port gigabit ethernet subsystem supports two external MAC ports and one internal CPPI port (communications port programming interface) or Host port.

Internal Port - One port (Port-0) is always reserved as the CPPI host port (CPDMA port) responsible for transfer of data between the CPU and the CPSW Peripheral core. Only the Host port can communicate with the CPDMA or R5F. Any incoming or outgoing data passes through the host port.

External Ports - The other (n-1) ports in CPSWNG are external MAC ports. E.g. CPSW3G has 2 MAC ports (port-1 and port-2) and one Host port (port-0). The external ports are MAC ports supporting Media Independent Interface (MII) like MII, Gigabit Media Independent Interface (GMII), Reduced Media Independent Interface (RMII), Reduced Gigabit Media Independent Interface (RGMII), Serial Gigabit Media Independent Interface (SGMII) and Quad Serial Gigabit Media Independent Interface (QSGMII).

The software configuration for the above sub-blocks is taken care of by the Syscfg auto-generated code and the Enet-LLD drivers. Based on the requirements of the application, these sub-blocks can be further configured in the application layer.

• CPDMA: In simple words, the CPDMA is responsible for transmission of data between the Host port and the R5F core. The CPDMA submodule is a packet DMA transfer controller. The Host CPPI Receive and Transmit interfaces can support line rate bandwidths on the ethernet ports. The Host Software communicates with network frames through what is called the CPDMA CPPI 3.0 and CBA 3.1 compliant packet DMA transfer controller host interface.
• ALE (Address Learning Engine): ALE is responsible for processing all the packets (based on the configurations of the ALE and incoming packet) and decide how/where the packet is forwarded. The ALE uses the incoming packet received port number, destination address, source address, length/type, and VLAN information to determine how the packet should be forwarded. The output of the ALE is a port-mask which is used to indicate the ports the packet should be forwarded to.
• Interrupt Controller: CPSW can fire interrupts from 6 different sources, which are used to handle the packets in the Enet-LLD driver (Software). Some examples include, THost (from Ethernet to host) non-paced level interrupt, interrupt to update per-port statistics, Miscellaneous level interrupt used for events such as Link status change, ECC error conditions, configuration changes, ALE events etc.
• Stats module: CPSW contains an in-built stats module which can store the per-port statistics. This module is useful for evaluating the performance of the application as well as debugging. CPSW stats module captures important data such as Frame counts for good and bad frames, Frame drop counts for various cases such as ALE overrun, FIFO overrun, Fragmentation errors, portmask drops, over/undersized frames, CRC and alignment errors etc.

• CPTS (Common Platform TimeSync): CPTS sub-module enables time-sync capabilities on the device. it enables event timestamping for every packet received or transmitted from CPSW. The TimeSync events are pushed to the CPSW FIFO
• MDIO (Management Data Input Output): The Management interface module implements the 802.3 serial management interface to interrogate and control external Ethernet PHY using a two-wire bus. Some key functionalities of the MDIO module are:
  • MDIO acts as the bridge between CPSW and PHY
  • MDIO module allows the CPSW to configure and control various aspects of the PHY devices such as link speed, Duplexity, power management etc.
  • MDIO also is used to monitor the status of each PHY, detecting Link up/down events.
  • MDIO is also responsible for auto-negotiation between CPSW and PHY

Apart from the above, the CPSW is also capable of features such as Packet classification, VLAN support, Policing/Rate limiting which are relevant to this app-note. Certain applications require the functionality of classifying ethernet packets before processing them. Different packet classes might have different processing logic or need a quicker turn-around time. CPSW can perform packet classification based on the following parameters:

• Destination MAC Address
• VLAN ID
• Priority (based on VLAN IDs)
• Ether-Type
• IP header fields
• Combination of any of the above

VLAN Support

Virtual LAN (VLAN) support provides a mechanism for logical segmentation of network traffic within a daisy-chained topology. By assigning different VLAN IDs to traffic originating from or destined for specific nodes or functional blocks, developers can isolate control traffic from data streams, prioritize safety-critical messages, or enable multi-tenant communication over the same physical network. This is particularly useful in industrial automation or modular robotic systems, where different subsystems need to securely share a common Ethernet backbone without interfering with each other's data domains. VLAN tagging also helps in managing broadcast domains and reducing unnecessary traffic propagation across the chain, improving determinism and bandwidth utilization. The CPSW and Enet-LLD driver supports ethernet packets having VLAN Tags and even hardware classification based on VLAN Tags

CPSW also supports InterVLAN and IntraVLAN routing in Hardware. This means that based on the VLAN tag in the ethernet packets, CPSW can decide which VLAN the packet needs to be forwarded to.

Rate Limiting

Policers and rate limiting mechanisms enable fine control over Ethernet traffic, particularly important in daisy-chained topologies. Policers monitor the rate of incoming or outgoing packets and enforce defined bandwidth limits by dropping or remarking packets that exceed configured thresholds. This ensures that no single device or application overwhelms the shared network medium, thereby preserving fairness and preventing congestion across the chain. Rate limiting can be applied at the ingress or egress of each MAC port to cap the bandwidth used by specific traffic classes or flows. In daisy-chained deployments, this helps maintain predictable latency and ensures that low-priority or non-critical traffic does not starve time-sensitive control or synchronization packets. When used in conjunction with QoS and VLAN tagging, policers and rate limiting provide a robust traffic management framework that enhances the reliability and determinism of multi-node industrial Ethernet systems.

Each AM261x node is configured at boot to initialize its CPSW, set up port VLAN IDs, populate the ALE table with MAC-to-port mappings, and run the network application logic based on its chain position.

Read more about CPSW here.