SFFS842A March   2024  – May 2025 TMCS1123-Q1 , TMCS1126-Q1 , TMCS1127-Q1 , TMCS1133-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 TMCS1123-Q1 Pin FMA
    2. 4.2 TMCS1126-Q1 Pin FMA
    3. 4.3 TMCS1127-Q1 Pin FMA
    4. 4.4 TMCS1133-Q1 Pin FMA
  7. 5Revision History

3 Failure Mode Distribution (FMD)

The failure mode distribution estimations covered in this document are for:

The failure mode distribution estimation comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 TMCS1123-Q1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
VOUT open (Hi-Z) 5
VOUT stuck (high or low) 25
VOUT functional, not in specification 25
VREF open (Hi-Z) 5
VREF stuck (high or low) 5
VREF functional, not in specification 5
OC false trip, failure to trip 15
ALERT false trip, failure to trip 15
Table 3-2 TMCS1126-Q1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
VOUT open (Hi-Z) 10
VOUT stuck (high or low) 20
VOUT functional, not in specification 20
VREF open (Hi-Z) 10
VREF stuck (high or low) 10
VREF functional, not in specification 10
OC false trip, failure to trip 20
Table 3-3 TMCS1127-Q1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
VOUT Stuck (high or low) 45
VOUT functional, not in specification 45
VOUT open (Hi-Z) 10
Table 3-4 TMCS1133-Q1 Die Failure Modes and Distribution
Die Failure Modes Failure Mode Distribution (%)
VOUT open (Hi-Z) 5
VOUT stuck (high or low) 30
VOUT functional, not in specification 30
OC false trip, failure to trip 15
ALERT false trip, failure to trip 20

The FMD in Table 3-1, Table 3-2, Table 3-3, and Table 3-4 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to IEC 61800-5-2:2016 if the following requirements are fulfilled:

  1. The signal isolation component is OVC III according to IEC 61800-5-1. If a SELV/PELV power supply is used, pollution degree 2/OVC II applies. All requirements of IEC 61800-5-1:2007, 4.3.6 apply.
  2. Measures are taken to ensure that an internal failure of the signal isolation component cannot result in excessive temperature of its insulating material.

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.