SFFSAJ9A June   2025  – September 2025 UCC27289

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 SOIC Package
    2. 2.2 VSON Package
  5. 3Failure Mode Distribution (FMD)
    1. 3.1 SOIC Package
    2. 3.2 VSON Package
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 SOIC Package
    2. 4.2 VSON Package
  7. 5Revision History

3.1 SOIC Package

The failure mode distribution estimation for UCC27289 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures resulting from misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
UCC27289
HO stuck high16.5
HO stuck low16.5
HO voltage out of specified range16.5
LO stuck high16.5
LO stuck low16.5
LO voltage out of specified range16.5
UVLO not functional1