SLAA941 March   2020 TUSS4440 , TUSS4470

 

  1.   TUSS44x0 Software Development Guide
    1.     Trademarks
    2. 1 Introduction to High-Level Software Flow
    3. 2 Main Energia Sketch File
      1. 2.1 MCU Initialization
      2. 2.2 TUSS44x0 Configuration
        1. 2.2.1 TUSS44x0 Odd Parity Calculation
        2. 2.2.2 TUSS44x0 Settings
          1. 2.2.2.1 Driver Settings
          2. 2.2.2.2 Receiver Settings
      3. 2.3 Read Ultrasonic Time-of-Flight
        1. 2.3.1 Run Time-of-Flight
        2. 2.3.2 Post-Process Data
        3. 2.3.3 Convert Time-of-Flight to Distance
    4. 3 Energia Examples
      1. 3.1 GetDistance.ino - COM Terminal Input Example
      2. 3.2 VOUT_ADC_Capture.ino - Standalone Example
    5. 4 References

2.2.1 TUSS44x0 Odd Parity Calculation

The parity bit ensures that the total number of 1-bits in the string is even or odd. Accordingly, there are two variants of parity bits: even parity bit and odd parity bit. In the case of even parity, for a given set of bits, the occurrences of bits whose value is 1 are counted. If that count is odd, the parity bit value is set to 1, making the total count of occurrences of 1s in the whole set (including the parity bit) an even number. If the count of 1s in a given set of bits is already even, the parity bit's value is 0. In the case of odd parity, the coding is reversed.

The frame odd parity bit value is required and used to ensure that data communicated between the master controller and the TUSS44x0 device has not been compromised or corrupted when transmitted or received. The odd parity bit value is generated by both the master and slave devices, and is included as bit 8 of the 16 bit frame. The odd-parity bit is always assumed to be a value of 0h prior to performing the odd parity bit calculation on the entire frame.

The master-to-slave (MCU to TUSS4470 over the SDI line) frame from MSbit to LSbit is: 1 RW bit, 6 bits for the register address, 1 ODD parity bit for entire SPI frame, 8 bits for data.

Odd Parity Bit Calculation Examples:

  • To read BPF_CONFIG_1 (address 0x10), the 16-bit SPI frame to read this register will be 0xA100, where 0xA1 in binary is 10100001:
    • 1 = Read High / Write Low bit
    • 010000 = Register Address
    • 1 = ODD Parity bit

    • In this case, there are only two bits set to '1' due to the read high bit and the register address, so the parity bit is set to '1' to create an odd number of '1' bits in the entire 16-bit frame.

  • To write a value of 0x11 to BPF_CONFIG_1, the 16-bit MOSI SPI frame is 0x2011, where 0x20 in binary is 00100000:
    • 0 = Read High / Write Low bit
    • 010000 = Register Address
    • 0 = ODD Parity bit
    and 0x11 is the data byte. In this case there at already three (odd number) bits set to '1' due to the register address and the data byte, so the ODD parity bit remains '0'.