SLAAE47A May   2022  – August 2022 DAC11001A , DAC11001B

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2DAC Error Sources
    1. 2.1 Offset Error
    2. 2.2 Gain Error
    3. 2.3 Integral Non Linearity (INL)
    4. 2.4 Noise Sources
  5. 3Error Sources from Reference
    1. 3.1 Initial Accuracy
    2. 3.2 Temperature Drift
    3. 3.3 Load Regulation Error
    4. 3.4 Line Regulation Error
    5. 3.5 0.1 - 10 Hz Peak-to-Peak Noise
    6. 3.6 Example Using REF7025
  6. 4Error Sources from Inverting and Non-Inverting Gain Stage
    1. 4.1 Input Offset Voltage Error
    2. 4.2 Input Offset Voltage Drift Error
    3. 4.3 Power Supply Rejection Ratio (PSRR) Error
    4. 4.4 Open Loop Gain Error
    5. 4.5 Resistor Tolerance Error
  7. 5Example Calculation using DAC11001A
  8. 6Error Summary
  9. 7References
  10. 8Revision History

3.3 Load Regulation Error

Load regulation is the measure of the variation in VREF as a function of load current and is specified either as a percentage or in parts-per-million (ppm) per milliampere (ppm/mA). It is calculated by dividing the relative change in VREF at minimum and maximum load currents by the range of the load current. Load regulation depends on both the design of the reference and the parasitic resistance separating it from the load, so the reference should be placed as close to the load as the PCB layout will allow.

Equation 7. Load Regulation Errorppm=Load Regulationppm/mA×Reference CurrentmA