SLAAE47A May   2022  – August 2022 DAC11001A , DAC11001B

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2DAC Error Sources
    1. 2.1 Offset Error
    2. 2.2 Gain Error
    3. 2.3 Integral Non Linearity (INL)
    4. 2.4 Noise Sources
  5. 3Error Sources from Reference
    1. 3.1 Initial Accuracy
    2. 3.2 Temperature Drift
    3. 3.3 Load Regulation Error
    4. 3.4 Line Regulation Error
    5. 3.5 0.1 - 10 Hz Peak-to-Peak Noise
    6. 3.6 Example Using REF7025
  6. 4Error Sources from Inverting and Non-Inverting Gain Stage
    1. 4.1 Input Offset Voltage Error
    2. 4.2 Input Offset Voltage Drift Error
    3. 4.3 Power Supply Rejection Ratio (PSRR) Error
    4. 4.4 Open Loop Gain Error
    5. 4.5 Resistor Tolerance Error
  7. 5Example Calculation using DAC11001A
  8. 6Error Summary
  9. 7References
  10. 8Revision History

4.1 Input Offset Voltage Error

Input offset voltage, VIO, is defined as the DC voltage that must be applied between the input terminals to force the quiescent DC output voltage to zero or some other level, if specified. If the input stage was perfectly symmetrical and the transistors were perfectly matched, VIO = 0 V.

Equation 9. I n p u t   o f f s e t   V o l a t g e   E r r o r p p m = V o s m a x V × O f f s e t   V o l t a g e   G a i n |   O p a m p ' s   O u t p u t   V o l a t g e V   |  
where,
Equation 10. O f f s e t   V o l t a g e   G a i n   =   1 +   R f R g  
Where Rf and Rg are the feedback and the gain setting registers respectively. Above equation is valid for both inverting and non-inverting amplifier stages.