SLAAE56 Application note

SLAAE56B November 2022 – August 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

3.6 Interrupt and Events Comparison

Interrupts and Exceptions

The MSPM0 and STM32G0 both register and map interrupt and exception vectors depending on the device available peripherals. A summary and comparison of the interrupt vectors for each family of devices is included in Table 3-10. A lower value of priority for an interrupt or exception is given higher precedence over interrupts with a higher priority value. For some of these vectors the priority is user-selectable, and for others, this is fixed.

In the MSPM0 and STM32G0, exceptions such as NMI, reset, and hard fault handlers are given negative priority values to indicate that these always have the highest precedence over peripheral interrupts. For peripherals with selectable interrupt priorities, up to four programmable priority levels are available on both families of devices.

Table 3-10 Interrupt Comparison

NVIC Number	STM32G0		MSPM0
	Interrupt/Exception	Priority	Interrupt/Exception	Priority
-	Reset	Fixed: -3	Reset	Fixed: -3
-	NMI Handler	Fixed: -2	NMI Handler	Fixed: -2
-	Hard Fault Handler	Fixed: -1	Hard Fault Handler	Fixed: -1
-	SVCall Handler	Selectable	SVCall Handler	Selectable
-	PendSV	Selectable	PendSV	Selectable
-	SysTick	Selectable	SysTick	Selectable
0	Window Watchdog Interrupt	Selectable	INT_GROUP0: WWDT0/1, DEBUGSS, FLASHCTL, WUC FSUBx, and SYSCTL	Selectable
1	Power Voltage Detector Interrupt	Selectable	INT_GROUP1: GPIOA/B/C, COMP0/1/2, TRNG⁽¹⁾	Selectable
2	RTC and Timestamp	Selectable	TIMG8⁽¹⁾	Selectable
3	Flash Global Interrupt	Selectable	UART3⁽¹⁾	Selectable
4	RCC Global Interrupt	Selectable	ADC0	Selectable
5	EXTI0 and EXTI1 interrupt	Selectable	ADC1⁽¹⁾	Selectable
6	EXTI2 and EXTI3 interrupt	Selectable	CANFD0⁽¹⁾	Selectable
7	EXTI4-EXTI15 interrupt	Selectable	DAC0⁽¹⁾	Selectable
8	UCPD1/UCPD2/USB	Selectable	TIMG9⁽¹⁾	Selectable
9	DMA1 Channel 1	Selectable	SPI0	Selectable
10	DMA1 Channel 2 and 3	Selectable	SPI1⁽¹⁾	Selectable
11	DMA1 Channel 4-6, and DMA2 Channel 1-5	Selectable	SPI2⁽¹⁾	Selectable
12	ADC and Comparator	Selectable	CANFD1⁽¹⁾	Selectable
13	Timer 1 (TIM1), Break, Update, Trigger, and Commutation	Selectable	UART1⁽¹⁾	Selectable
14	TIM1 Capture Compare	Selectable	UART4⁽¹⁾	Selectable
15	TIM2 global interrupts	Selectable	UART0	Selectable
16	TIM3 and TIM4 global interrupts	Selectable	TIMG0⁽¹⁾	Selectable
17	TIM6, LPTIM1, and DAC interrupts	Selectable	TIMG6⁽¹⁾	Selectable
18	TIM6 and LPTIM2 global interrupts	Selectable	TIMA0⁽¹⁾	Selectable
19	TIM14 global interrupts	Selectable	TIMA1	Selectable
20	TIM15 global interrupts	Selectable	TIMG7⁽¹⁾	Selectable
21	TIM16 and FDCAN0 global interrupts	Selectable	TIMG12⁽¹⁾	Selectable
22	TIM17 and FDCAN1 global interrupts	Selectable	TIMG14⁽¹⁾	Selectable
23	12C1 global interrupts	Selectable	UART5⁽¹⁾	Selectable
24	I2C2 and I2C3 global interrupts	Selectable	I2C0	Selectable
25	SPI1 global interrupts	Selectable	I2C1	Selectable
26	SPI2 and SPI3 global interrupts	Selectable	I2C2⁽¹⁾	Selectable
27	USART1 global interrupts	Selectable	UART7⁽¹⁾	Selectable
28	USART2 and LPUART2 global interrupts	Selectable	AES⁽¹⁾	Selectable
29	USART 3-6 and LPUART1 global interrupts	Selectable	UART6⁽¹⁾	Selectable
30	CEC global interrupts	Selectable	RTC⁽¹⁾	Selectable
31	AES and RNG global interrupts	Selectable	DMA	Selectable

(1) Listed interrupts are specific to the MSPM0G3519. Check the device-specific data sheet for exact specifications.

Event Handler and EXTI (Extended Interrupt and Event Controller)

The MSPM0 devices include a dedicated event manager peripheral, which extends the concept of the NVIC to allow digital events from a peripheral to be transferred to the CPU as interrupts, to the DMA as a trigger, or to another peripheral to trigger a hardware action. The event manager can also perform handshaking with the power management and clock unit (PMCU), to make sure that the necessary clock and power domain are present for triggered event actions to take place.

Figure 3-2 Generic Event Route

In the MSPM0 event manager, the peripheral that generates the event is known as a publisher, and the peripheral, DMA, or CPU that acts based on the publisher is known as the subscriber. The potential combinations of available publisher and subscriber are extremely flexible and can be used when migrating software to replace functionality previously handled by interrupt vectors and the CPU, to bypass the CPU entirely. For example, an I²C-to-UART bridge can previously have triggered a UART transmission upon receipt of an I²C STOP, using an ISR to set a flag, or load the UART TX buffer directly. With the MSPM0 Event handler, the I²C transaction complete event can trigger the DMA to load the UART TX buffer directly, and therefore eliminate the need for any action by the CPU.

See the Events section of the MSPM0G technical reference manual or the MSPM0L technical reference manual to get more details on the use of the event handler in MSPM0.

Not to be confused with the MSPM0 event handler, the STM32G0 family of devices implement an extended interrupt and event controller (EXTI), which allows for the system wake from STOP mode through configurable events from IOs or peripherals. The wakeup features of the STM32G0 EXTI can be best replicated in MSPM0 using the IO wakeup features (see the IOMUX section of the MSPM0 technical reference manuals) and GPIO FastWake (see the GPIO section of the MSPM0 technical reference manuals). If the wakeup is for a single action, the Event handler peripheral is capable of requesting necessary PMCU resources for a peripheral operation to occur, and returning to the applicable low power mode after.