SLAAE56B November   2022  – August 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM32 MCUs to MSPM0 MCUs
    3. 1.3 Pin to Pin Comparison of STM32 MCUs to MSPM0 MCUs
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 CubeIDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 CubeMX vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
    6. 3.6 Interrupt and Events Comparison
    7. 3.7 Debug and Programming Comparison
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6Summary
  10. 7References
  11. 8Revision History

3.2.1 Flash Features

The MSPM0 and STM32G0 family of MCUs feature nonvolatile flash memory used for storing executable program code and application data.

Table 3-2 Comparison of Flash Feature
FeaturesSTM32G0MSPM0
Flash memory

STM32G0B1xx, G0C1xx (up to 512KB)

STM32G071xx, G081xx (up to 128KB)

STM32G031xx, G041xx, G051xx, G061xx (up to 64KB)

MSPM0Gxx ranges 512KB to 32KB

MSPM0Lxx ranges 256KB to 8KB

MSPM0Cxx ranges 64KB to 8KB

MSPM0Hxx ranges 64KB to 8KB

Memory organization

1 bank – devices up to 128KB

2 banks – devices with >128KB

1 bank – devices up to 256KB

2 banks – devices with >256KB

Flash wait states

0 (HCLK ≤ 24 MHz)

1 (HCLK ≤ 48 MHz)

2 (HCLK ≤ 64 MHz)

0 (MCLK, CPUCLK ≤ 24 MHz)

1 (MCLK, CPUCLK ≤ 48 MHz)

2 (MCLK, CPUCLK ≤ 80 MHz)

Flash word size64 bits plus 8 ECC bits64 bits plus 8 ECC bits
Programming resolutionSingle word sizeSingle word, 32-, 16-, or 8-bit (byte)
Multi-word programming32 words (256 bytes)2, 4, or 8 words (up to 64 bytes)
Erase

Page size = 2KB

Bank erase (single bank)

Mass erase (all banks)

Sector size = 1KB

Bank erase (up to 256KB)

Write protectionYes (2 write protection areas per bank)Yes, static and dynamic
Read protectionYesYes
Flash memory read operations64-bit flash word size plus 8 ECC bitsSame – if optional ECC is present
Flash memory write operations64-bit flash word size plus 8 ECC bitsSame – if optional ECC is present
Error code correction (ECC)8 bits for 64 bitsSame – if optional ECC is present
Securable memory areaYes, main memoryNo
Info memoryYesYes (NONMAIN)
OTP data region1KBNo
PrefetchYesYes
CPU instruction cache

Two 64-bit cache lines (16 bytes)

4x 32-bit instructions or

8x 16-bit instructions

MSPM0Gx:

Four 64-bit cache lines (32 bytes) 8x 32-bit instructions or

16x 16-bit instructions

MSPM0Lx/Cx/Hx:

Two 64-bit cache lines 4x 32-bit instructions or

8x 16-bit instructions

In addition to the flash memory features listed in the previous table, the MSPM0 flash memory also has the following features:

  • In-circuit program and erase supported across the entire supply voltage range
  • Internal programming voltage generation
  • Support for EEPROM emulation with up to 100 000 program/erase cycles on the lower 32KB of the flash memory, with up to 10 000 program/erase cycles on the remaining flash memory (devices with 32KB support 100 000 cycles on the entire flash memory)