SLAAE84B March   2023  – September 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3215 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   1
  2. 1 Description
  3. 2 Required Peripherals
  4. 3 Design Steps
  5. 4 Design Considerations
  6. 5 Software Flow Chart
  7. 6 Design Results
  8. 7 Additional Resources
  9. 8 E2E
  10. 9 Trademarks
  11. 10Revision History

Required Peripherals

This application requires the integrated ADC and DMA. The internal VREF is an additional option for the ADC reference, if a different reference value is required.

Table 2-1 Required Peripherals
Subblock Functionality Peripheral Use Notes
Analog Signal Capture ADC Called ADC12_0_INST in code
Moving memory DMA Full featured DMA channel is required to utilize the PREIRQ functionality. The example can be altered to work without the PREIRQ.