SLAAE84B March   2023  – September 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   1
  2. 1 Description
  3. 2 Required Peripherals
  4. 3 Design Steps
  5. 4 Design Considerations
  6. 5 Software Flow Chart
  7. 6 Design Results
  8. 7 Additional Resources
  9. 8 E2E
  10. 9 Trademarks
  11. 10Revision History

6 Design Results

The following contents show the results of the code executing. Figure 6-1 shows the results of the buffers after the first execution of the main loop. After the buffer is filled, the code swaps the DMA destination to the second buffer and the CPU is now free to utilize data in the first buffer.

Buffers After First Pass Figure 6-1 Buffers After First Pass

Figure 6-2 shows the results of the second buffer after the second execution of the main loop. After the buffer is filled, the code swaps the DMA destination back to the first buffer and now the CPU can use the data in the second buffer.

Buffers After Second Pass Figure 6-2 Buffers After Second Pass