SLAAED5 june   2023 AFE11612-SEP , INA240-SEP , OPA4H199-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. LDMOS and GaN Power Amplifier FET PA Basics
  5. VGS Compensation
  6. Sequencing
  7. An Integrated PA Biasing Solution
  8. Negative GaN Biasing
  9. VDRAIN Switching Circuit
  10. Controlled Gate Sequencing Circuit
  11. VDRAIN Monitoring
  12. IDQ Monitoring
  13. 10External Negative Power Supply Monitoring
  14. 11PA Temperature Monitoring
  15. 12Summary
  16. 13References

Sequencing

Powering the PA on and off in a controlled routine is necessary to prevent the VGS voltage from being too high when the VDRAIN is applied. Such a state causes the PA to operate in saturation mode which may result in thermal damage in the PA or the board it is mounted on. Powering on a PA requires the following steps:

  1. First, apply the VGS signal to the PA. The VGS voltage must transition to the VGS pinch-off voltage or lower. This ensures that when the VDRAIN voltage is applied, the gate is already low.
  2. Next, enable the drain voltage supply and allow the VDRAIN to be powered to the nominal value (50 V, for example). As the VGS is at the pinch-off voltage, IDS must be minimal.
  3. After the VDRAIN is applied, increase the VGS bias voltage to set the desired power output of the PA.
  4. Finally, enable the RF signal. This allows the PA to transmit a signal.
GUID-79DA69AC-F414-4D8C-B5D2-10ADA3069F01-low.gifFigure 3-1 GaN Power Sequencing

The PA can be safely shut down by reversing the power-on steps.

  1. Disable the RF signal from the PA.
  2. Reduce the VGS voltage to the pinch-off value, eliminating the power output of the PA.
  3. Disable the VDRAIN voltage by sending a disable signal to the drain supply.
  4. Finally, the VGS voltage can be allowed to collapse to ground as the PA is fully disabled.