Timer period: The timer clock source,
clock divider, and prescaler were chosen to allow for a watchdog timer period
between 30us and 2s. The macros were defined using the initial timer period of
1s to calculate load values for 500ms, 250ms, 125ms, 100ms, 50ms, 25ms, 12.5ms,
and 10ms.
Reset pulse length: The pulse length of
the output signal is by default 1s, utilizing the DriverLib delay_cycles
function. The macros were defined using the initial 24,000,000 cycle delay (1s)
to calculate the number of cycles to delay for 20ms, 10ms, 5ms, 2.5ms, and
2ms.