SLAAET2A March   2025  – September 2025 TAS2120 , TAS2320 , TAS2572 , TAS2574

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 What is Y-Bridge
  6. 3 Benefits of Y-Bridge
  7. 4 Configuration of Y-Bridge
  8. 5 Y-Bridge Thresholds and Hysteresis Registers
  9. 6 1S, 2S and External PVDD Mode
  10. 7 Efficiency Improvement for Different Use Cases
  11. 8 Summary
  12. 9 References
  13. 10Revision History

6 1S, 2S and External PVDD Mode

The TAS2572, TAS2574, and TAS2120 devices feature an integrated Class-H boost circuit as well as supporting 1S, 2S, and External PVDD mode. As a result, the Y-Bridge PVDD voltage can vary depending on the specific use case and the application circuit. PVDD voltage can be same as the voltage on the VBAT pin when there is no power demand for the boost voltage (boost by-pass mode), or this can come from an external fixed supply (if a high voltage rail is already available in the system), or this can also come from an external boost circuitry. Therefore, depending on the 1S, 2S and external PVDD mode, the PVDD high voltage can vary.

In boost bypass mode, where the boost is not required, the PVDD voltage can be identical to the VBAT voltage (ranging from 2.5V to 5.5V). In this case, PVDD = VBAT.

In integrated boost mode, the PVDD voltage is determined by the internally generated boost output, which is derived from the VBAT supply. Here, PVDD = internal boost output voltage.

In external PVDD mode, the PVDD voltage is sourced either from a fixed external power supply or by an external boost output. This mode is particularly applicable to the TAS2320 device, which does not feature an integrated boost circuit.