SLAAET2A March   2025  – September 2025 TAS2120 , TAS2320 , TAS2572 , TAS2574

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 What is Y-Bridge
  6. 3 Benefits of Y-Bridge
  7. 4 Configuration of Y-Bridge
  8. 5 Y-Bridge Thresholds and Hysteresis Registers
  9. 6 1S, 2S and External PVDD Mode
  10. 7 Efficiency Improvement for Different Use Cases
  11. 8 Summary
  12. 9 References
  13. 10Revision History

4 Configuration of Y-Bridge

This application note details the process of configuring the Y-Bridge registers for the TAS2x20 and TAS257x device families. Both families utilize the Y-Bridge configuration to enhance efficiency during audio playback. When the feature is enabled using EN_Y_BRIDGE_MODE set to high, the device can automatically select the output voltage to switch the output PWM.

Table 4-1 VDD Y-Bridge Mode Configuration
EN_Y_BRIDGE_MODE Configuration
0 Y-Bridge mode is disabled
1 (default) Y-Bridge mode is enabled

When the audio signal level is low, the output can switch at 1.8V (VDD) to enable higher system-level efficiency by reducing the class-D output switching voltage. Conversely, when the audio signal level is high, the output switches at PVDD to make sure the required output power level is met.