SLAAEV0 July   2026 BQ79616-Q1

 

  1.   1
  2.   Abstract
  3. 1Basic Principle of Reverse Wake-up for BQ79616
    1. 1.1 Basic Principle of Reverse Wake-up Implemented by BQ79616 and BQ79600
    2. 1.2 OVUVOTUT Function of BQ79616
    3. 1.3 Logic for BQ79600 to Implement Reverse Wake-up
  4. 2How to Configure BQ79616 and BQ79600 to Achieve Reverse Wake-up Function
    1. 2.1 Configuration for BQ79616 to Implement Reverse Wake-up Function
    2. 2.2 Configuration for BQ79600 to Implement Reverse Wake-up Function
    3. 2.3 Other Configurations for BQ79600 and BQ79616 Prior to Entering Sleep
  5. 3Testing of Reverse Wake-up Based on EVM Board
    1. 3.1 Reverse Wake-up Test with BQ79600 Operating in Sleep Mode
    2. 3.2 Reverse Wake-up Test with BQ79600 Operating in Shutdown Mode
  6. 4Summary
  7. 5References

3.2 Reverse Wake-up Test with BQ79600 Operating in Shutdown Mode

Next, conduct the reverse wake-up test under BQ79600 Shutdown mode. It is required to enable the SNIF function of the BQ79600, and simultaneously mask the Heartbeat detection of the first AFE. After waking up the system and addressing, run the following code:

#First wake up all chips, perform addressing and configure GPIOs, the test uses GPIO4 as the OT channel

# GPIO4 configured as ADC input and OTUT

90 01 00 0F 08 E1 D7

# Enable TSREF

90 01 03 0A 01 D2 81

# ADC_GO, enable GPIO configuration

90 01 03 0D 0E 90 B5

# Enable Heartbeat and Fault tone for BQ79616

90 01 00 02 03 A4 80

# OV threshold=2700mV

90 01 00 09 02 62 70

# UV threshold=1200mV

90 01 00 0A 00 E3 41

# CELL9-16 ENABLE

90 01 00 0C 00 E0 E1

# CELL0-8 ENABLE

90 01 00 0D 00 E1 71

# UT 66%,OT 10%

90 01 00 0B 00 E2 D1

# OVUV-GO Round robin with all cells

90 01 03 2C 05 C9 22

# OTUT-GO Round robin with all cells

90 01 03 2D 05 C8 B2

# Enable HB and TONE_RX_EN for BQ79600

90 00 20 01 35 24 50

# If manipulating 0x2001 or 0x2020, CONF_MON_GO must be sent once while resetting RST_REG.

90 00 20 00 20 E4 0F

# Reset INH of BQ79600

90 00 20 02 03 A4 B6

# Re-enable INH of BQ79600

90 00 20 02 00 E4 B7

#enable snif

90 00 20 01 94 E5 E8

# Mask all faults of BQ79616 except OVUVOTUT, Heartbeat and Fault tone

91 01 00 16 87 73 E2 8B

#mask HB fault of S1

90 01 00 17 77 AA 37

# Reset all faults for BQ79616

91 01 03 31 FF FF 71 61

# Reset all faults for BQ79600

90 00 20 30 FF B1 97

# All BQ79616 enter sleep mode

B0 03 09 04 D1 77

# 600 go to shutdown

90 00 03 09 08 13 8B

After running the example code, the BQ79616 is in Sleep mode and the BQ79600 is in Shutdown mode. Adjust the cell voltage or temperature or disconnect the communication line to trigger an OVUVOTUT or Heartbeat fault. The logic analyzer data of the test results are shown in Figure 3-4 and Figure 3-5:

Wherein:

  • D0: 600TX is the TX signal of the UART for communication between the BQ79600 and the MCU.
  • D1: 600RX is the RX signal of the UART for communication between the BQ79600 and the MCU.
  • D2: S1 COMLP is the COML port of the first BQ79616.
  • D3: 600COML is the COML port of the BQ79600.
  • D4: 600CVDD is the CVDD voltage of the BQ79600, used to characterize whether the BQ79600 is in the active state.
  • D5: INH is the INH pin of the BQ79600.
Logic Analyzer Data for Reverse Wake-up Implemented with BQ79600 Operating in Shutdown ModeFigure 3-4 Logic Analyzer Data for Reverse Wake-up Implemented with BQ79600 Operating in Shutdown Mode

It can be observed that,

  1. At time t0, the BQ79616 enters Sleep mode, the BQ79600 enters Shutdown mode, and CVDD is pulled low.
  2. Before time t1, the BQ79616 transmits a Heartbeat tone to the subsequent chips every 400ms.
  3. At time t1, an OVUVOTUT or Heartbeat tone fail fault is artificially injected. At this moment, after detecting the fault, the BQ79616 immediately begins transmitting a Fault tone.
  4. Upon receiving the Fault tone, the BQ79600 enters VALIDATE mode and awaits the second Fault tone.
  5. At time t2, the BQ79600 receives the second Fault tone, and INH is pulled high.
Enlarged View of Logic Analyzer DataFigure 3-5 Enlarged View of Logic Analyzer Data