SLASEX7C June   2021  – January 2026 TAS5828M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
        2. 7.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Low EMI Modes
        1. 7.4.3.1 Spread Spectrum
        2. 7.4.3.2 Channel to Channel Phase Shift
        3. 7.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 7.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 7.4.3.3.2 Phase Synchronization With GPIO
      4. 7.4.4 Thermal Foldback
      5. 7.4.5 Device State Control
      6. 7.4.6 Device Modulation
        1. 7.4.6.1 BD Modulation
        2. 7.4.6.2 1SPW Modulation
        3. 7.4.6.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Hardware Control Mode
      3. 7.5.3 I2 C Target Address
        1. 7.5.3.1 Random Write
        2. 7.5.3.2 Sequential Write
        3. 7.5.3.3 Random Read
        4. 7.5.3.4 Sequential Read
        5. 7.5.3.5 DSP Memory Book, Page and BQ update
        6. 7.5.3.6 Checksum
          1. 7.5.3.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.3.6.2 Exclusive or (XOR) Checksum
      4. 7.5.4 Control via Software
        1. 7.5.4.1 Startup Procedures
        2. 7.5.4.2 Shutdown Procedures
      5. 7.5.5 Protection and Monitoring
        1. 7.5.5.1 Overcurrent Limit (Cycle-By-Cycle)
        2. 7.5.5.2 Overcurrent Shutdown (OCSD)
        3. 7.5.5.3 DC Detect Error
        4. 7.5.5.4 Overtemperature Shutdown (OTSD)
        5. 7.5.5.5 PVDD Overvoltage and Undervoltage Error
        6. 7.5.5.6 PVDD Drop Detection
        7. 7.5.5.7 Clock Fault
  9. 8 Register Maps
    1. 8.1 CONTROL PORT Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor Selections
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
      5. 9.2.5 Advanced 2.1 System (Two TAS5828M Devices)
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 DVDD Supply
      2. 9.3.2 PVDD Supply
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 General Guidelines for Audio Amplifiers
        2. 9.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 9.4.1.3 Optimizing Thermal Performance
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TAS5828M DAD (TSSOP) Package, 32-Pin PadUp, Software Mode, Top View Figure 4-1 DAD (TSSOP) Package, 32-Pin PadUp, Software Mode, Top View
Table 4-1 Pin Functions - Software Mode
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 1 G Analog ground.
AVDD 2 P Internally regulated 5V analog supply voltage. This pin must not be used to drive external devices.
GVDD 3 P Gate drive internal regulator output. This pin must not be used to drive external devices.
PDN 4 DI Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
SCL 5 DI I2C serial control clock input.
SDA 6 DI/O I2C serial control data interface input/output.
SDIN 7 DI Data line to the serial data port.
BCLK 8 DI Bit clock for the digital signal that is active on the input data line of the serial data port.
LRCLK 9 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
GPIO2 10 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x62h). Can be configured to be open drain output or push-pull output.
GPIO1 11 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x61h). Can be configured to be open drain output or push-pull output.
GPIO0 12 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x63h). Can be configured to be open drain output or push-pull output.
ADR 13 AI A table of resistor value (Pull down to GND) decides the device I2C address. See Table 7-7.
VR_DIG 14 P Internally regulated 1.5V digital supply voltage. This pin must not be used to drive external devices.
DVDD 15 P 3.3V or 1.8V digital power supply.
DGND 16 G Digital ground.
PVDD 17 P PVDD voltage input.
18 P
31 P
32 P
PGND 21 G Ground reference for power device circuitry. Connect this pin to system ground.
22 G
27 G
28 G
OUT_A+ 19 PO Positive pin for differential speaker amplifier output A.
BST_A+ 20 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+.
OUT_A- 23 PO Negative pin for differential speaker amplifier output A.
BST_A- 24 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-.
BST_B- 25 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-.
OUT_B- 26 PO Negative pin for differential speaker amplifier output B.
BST_B+ 29 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+.
OUT_B+ 30 PO Positive pin for differential speaker amplifier output B.
PowerPAD™ P Ground, connect to grounded heat sink for best system performance.
(1) AI = Analog input, PO = Power output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0V)
TAS5828M DAD (TSSOP) Package, 32-Pin PadUp, Hardware Mode,Top View Figure 4-2 DAD (TSSOP) Package, 32-Pin PadUp, Hardware Mode,Top View
Table 4-2 Pin Functions - Hardware Mode
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 1 G Analog ground.
AVDD 2 P Internally regulated 5V analog supply voltage. This pin must not be used to drive external devices.
GVDD 3 P Gate drive internal regulator output. This pin must not be used to drive external devices.
PDN 4 DI Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
HW_SEL0 5 DI Analog gain and BTL/PBTL mode selection in Hardware Mode . Pull up to DVDD or Pull down to ground with different resistor. See Table 7-6.
HW_SEL1 6 DI PWM Switching Frequency and Spread Spectrum Enable/Disable selection in Hardware Mode. Pull up to DVDD or Pull down to ground with different resistor. See Table 7-5.
SDIN 7 DI Data line to the serial data port.
BCLK 8 DI Bit clock for the digital signal that is active on the input data line of the serial data port.
LRCLK 9 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
MUTE 10 DI Speaker amplifier Mute. Which must be pulled low (connect to DGND) to MUTE the device and pulled high (connected to DVDD) to exit MUTE state. In Mute state, device output keep in Hi-Z state.
FAULT 11 DO Fault terminal,which is pulled LOW when an internal fault occurs.
PD_DET 12 DO PVDD Drop detection, which is pulled LOW when the PVDD drop below 8V.
HW_MODE 13 AI Connect to DVDD directly to maintain device enter into Hardware Control Mode.
VR_DIG 14 P Internally regulated 1.5V digital supply voltage. This pin must not be used to drive external devices.
DVDD 15 P 3.3V or 1.8V digital power supply.
DGND 16 G Digital ground.
PVDD 17 P PVDD voltage input.
18 P
31 P
32 P
PGND 21 G Ground reference for power device circuitry. Connect this pin to system ground.
22 G
27 G
28 G
OUT_A+ 19 PO Positive pin for differential speaker amplifier output A.
BST_A+ 20 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+.
OUT_A- 23 PO Negative pin for differential speaker amplifier output A.
BST_A- 24 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-.
BST_B- 25 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-.
OUT_B- 26 PO Negative pin for differential speaker amplifier output B.
BST_B+ 29 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+.
OUT_B+ 30 PO Positive pin for differential speaker amplifier output B.
PowerPAD™ P Ground, connect to grounded heat sink for best system performance.
(1) AI = Analog input, PO = Power output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0V)