SLASFD4A August   2024  – July 2026 TAS2020

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Thermal Protection
      5. 6.4.5 Clocks and PLL
        1. 6.4.5.1 Auto clock based wakeup and clock errors
      6. 6.4.6 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.2 Faults and Status

During power-up sequencing, the power-on-reset circuit (POR) monitors the VDD and IOVDD pins and holds device in reset (including all the configuration registers) until the supplies are valid. Any supply voltage dip on VDD or IOVDD below the UVLO voltage thresholds resets the device immediately along with all the register configurations.

During operation modes, the device monitors internal device status and fault conditions and can notify the host of error and status conditions using the IRQZ interrupt pin and internal I2C based interrupt registers. The interrupt generation in IRQZ pin can be masked by configuring the corresponding Interrupt mask register bit.

Table 6-11 lists the different faults and interrupts that the device monitors and the corresponding configuration bits to enable/disable the interrupt generation and reading the I2C interrupt status

Table 6-11 Faults and Interrupts
Category Interrupt Interrupt Mask register bit Default Mask status Interrupt Latched status bit
Limiter & Brown out protection Section 6.4.2.4 Brownout detected INT_MASK0[3] Not Masked INT_LTCH0[3]
BOP Active INT_MASK0[2] Not Masked INT_LTCH0[2]
BOP infinite hold INT_MASK0[7] Not Masked INT_LTCH0[7]
Limiter Active INT_MASK0[4] Not Masked INT_LTCH0[4]
Limiter attenuation INT_MASK0[6] Not Masked INT_LTCH0[6]
Supply below inflection point INT_MASK0[5] Not Masked INT_LTCH0[5]
Supply Voltage Monitors PVDD Over voltage INT_MASK3[2] Not Masked INT_LTCH3[2]
PVDD Under voltage INT_MASK1[7] Not Masked INT_LTCH1[7]
Thermal protectionSection 6.4.4 Thermal warning at 135C INT_MASK1[4] Masked INT_LTCH1[4]
Thermal warning at 125C INT_MASK1[3] Masked INT_LTCH1[3]
Thermal warning at 115C INT_MASK1[2] Masked INT_LTCH1[2]
Thermal warning at 105C INT_MASK1[1] Masked INT_LTCH1[1]
Over temperature error INT_MASK3[7] Not Masked INT_LTCH3[7]
Clock protection Watchdog expiry INT_MASK2[7] Not Masked INT_LTCH2[7]
Frame out of sync INT_MASK2[5] Masked INT_LTCH2[5]
PLL clock error INT_MASK2[4] Not Masked INT_LTCH2[4]
TDM clock error INT_MASK2[3] Masked INT_LTCH2[3]
Pre-Power-up Clock error INT_MASK4[2] Not Masked INT_LTCH4[2]
Clock ratio change error INT_MASK2[2] Masked INT_LTCH2[2]
Fs change error INT_MASK2[1] Masked INT_LTCH2[1]
Fs invalid error INT_MASK2[0] Masked INT_LTCH2[0]
Frame out of sync INT_MASK2[5] Masked INT_LTCH2[5]
Internal PLL Clock error INT_MASK2[4] Not Masked INT_LTCH2[4]
Digital watchdog INT_MASK2[7] Not Masked INT_LTCH2[7]
Other Protections & Status Class-D Over current error INT_MASK3[3] Not Masked INT_LTCH3[3]
Device Active INT_MASK0[1] Masked INT_LTCH0[1]