SLASFD4A August   2024  – July 2026 TAS2020

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4 Thermal Protection
      5. 6.4.5 Clocks and PLL
        1. 6.4.5.1 Auto clock based wakeup and clock errors
      6. 6.4.6 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE 0 Registers
    2. 7.2 PAGE 1 Registers
    3. 7.3 PAGE 2 Registers
    4. 7.4 PAGE 4 Registers
    5. 7.5 PAGE 5 Registers
    6. 7.6 PAGE 6 Registers
    7. 7.7 PAGE 7 Registers
    8. 7.8 PAGE 8 Registers
    9. 7.9 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 EMI Passive Devices
        3. 8.2.2.3 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.1.2 Hardware Config Modes

The TAS2020 device can operate in a Pin control based HW Mode depending on the resistor terminations used for Select Pin1 to Select Pin5. Pin control based HW Mode behavior of the device is designed to simplify device configuration without using any software based configurations through I2C communication.

Table 6-2 Select Pin Functionalities
Select Pin Name Functionality
SEL1 Amplifier gain setting with volume ramp enable/disable option
SEL2 I2S, TDM, Left justified selection
SEL3 Data valid rising/falling edge selection
SEL4 Y-bridge threshold configuration
Table 6-3 SEL1 HW Mode configuration
SEL1 Connection Amplifier Gain Volume Ramp
Direct Short to GND Configured through I2C Configured through I2C
1.2kΩ to GND 6dBV Disabled
1.2kΩ to PVDD 12dBV Disabled
5kΩ to PVDD 6dBV Enabled
24kΩ to GND 12dBV Enabled
Table 6-4 SEL2 HW Mode configuration
SEL2 Connection Configuration
Direct Short to GND I2S L or TDM0
330Ω to IOVDD I2S R or TDM1
Direct Short to IOVDD I2S (L+R)/2 or TDM2
1.2kΩ to GND Left-Justified L or TDM3
1.2kΩ to IOVDD Left-Justified R or TDM4
5kΩ to GND Left-Justified (L+R)/2 or TDM5
5kΩ to IOVDD I2S L or TDM6
24kΩ to GND I2S R or TDM7
24kΩ to IOVDD Reserved
Table 6-5 SEL3 HW Mode configuration
SEL3 Connection Configuration
Direct Short to GND Data valid on rising edge
Direct Short to IOVDD Data valid on falling edge
Table 6-6 SEL4 HW Mode configuration
SEL4 Connection Configuration
Direct Short to GND Y-bridge threshold of 80mW
Direct Short to IOVDD Y-bridge threshold of 40mW
24kΩ to IOVDD Y-bridge threshold of 1mW